Fix clock enables with bit-extends, #2299.

Changes

@@ -42,6 +42,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix reduction OR on wide data, broke in v4.026, #2300. [Jack Koenig]
 
+****  Fix clock enables with bit-extends, #2299. [Marco Widmer]
+
 
 * Verilator 4.032 2020-04-04
 

src/V3Gate.cpp

@@ -1497,7 +1497,7 @@ private:
         vvertexp->iterateCurrentOutEdges(*this, VNUser(&nextState));
         if (vsp->varp()->width() > 1) --m_seen_clk_vectors;
         vsp->user2(false);
-        return VNUser(0);
+        return VNUser(0);  // Unused
     }
 
     virtual VNUser visit(GateLogicVertex* lvertexp, VNUser vu) {
@@ -1506,6 +1506,7 @@ private:
         if (const AstAssignW* assignp = VN_CAST(lvertexp->nodep(), AssignW)) {
             UINFO(9, "CLK DECOMP Logic (off = " << clk_offset << ") - " << lvertexp << " : "
                                                 << m_clk_vsp << endl);
+            // RHS
             if (AstSel* rselp = VN_CAST(assignp->rhsp(), Sel)) {
                 if (VN_IS(rselp->lsbp(), Const) && VN_IS(rselp->widthp(), Const)) {
                     if (clk_offset < rselp->lsbConst() || clk_offset > rselp->msbConst()) {
@@ -1521,11 +1522,17 @@ private:
             } else if (AstConcat* catp = VN_CAST(assignp->rhsp(), Concat)) {
                 UINFO(9, "CLK DECOMP Concat searching - " << assignp->lhsp() << endl);
                 int concat_offset;
-                if (!m_concat_visitor.concatOffset(catp, currState->m_last_vsp, concat_offset)) {
+                if (!m_concat_visitor.concatOffset(catp, currState->m_last_vsp,
+                                                   concat_offset /*ref*/)) {
                     return VNUser(0);
                 }
                 clk_offset += concat_offset;
+            } else if (VN_IS(assignp->rhsp(), VarRef)) {
+                UINFO(9, "CLK DECOMP VarRef searching - " << assignp->lhsp() << endl);
+            } else {
+                return VNUser(0);
             }
+            // LHS
             if (const AstSel* lselp = VN_CAST(assignp->lhsp(), Sel)) {
                 if (VN_IS(lselp->lsbp(), Const) && VN_IS(lselp->widthp(), Const)) {
                     clk_offset += lselp->lsbConst();
@@ -1538,8 +1545,8 @@ private:
                         UINFO(9, "Should only make it here with clk_offset = 0" << endl);
                         return VNUser(0);
                     }
-                    UINFO(9, "CLK DECOMP Connecting - " << assignp->lhsp() << " <-> " << m_clk_vsp
-                                                        << endl);
+                    UINFO(9, "CLK DECOMP Connecting - " << assignp->lhsp() << endl);
+                    UINFO(9, "                   to - " << m_clk_vsp << endl);
                     AstNode* rhsp = assignp->rhsp();
                     rhsp->replaceWith(new AstVarRef(rhsp->fileline(), m_clk_vsp, false));
                     for (V3GraphEdge* edgep = lvertexp->inBeginp(); edgep;) {
@@ -1548,6 +1555,8 @@ private:
                     new V3GraphEdge(m_graphp, m_clk_vvertexp, lvertexp, 1);
                     m_total_decomposed_clk_vectors++;
                 }
+            } else {
+                return VNUser(0);
             }
             GateClkDecompState nextState(clk_offset, currState->m_last_vsp);
             return lvertexp->iterateCurrentOutEdges(*this, VNUser(&nextState));

test_regress/t/t_clk_gate_ext.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_clk_gate_ext.v

@@ -0,0 +1,25 @@
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   reg   clk_en = 1'b0;
+   wire  clk_gated = clk & clk_en;
+   wire [1:0] clks = {1'b0, clk_gated};
+
+   always @(posedge clks[0]) begin
+      $display("ERROR: clks[0] should not be active!");
+      $stop;
+   end
+
+   int cyc = 0;
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule