Fix combining different-width parameters (#2484).

Changes

@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ***   Fix arrayed interfaces, broke in 4.038 (#2468). [Josh Redford]
 
+****  Fix combining different-width parameters (#2484). [abirkmanis]
+
 
 * Verilator 4.038 2020-07-11
 

src/V3Param.cpp

@@ -635,7 +635,7 @@ void ParamVisitor::visitCell(AstCell* nodep, const string& hierName) {
                         // This prevents making additional modules, and makes coverage more
                         // obvious as it won't show up under a unique module page name.
                     } else if (exprp->num().isDouble() || exprp->num().isString()
-                               || exprp->num().isFourState()) {
+                               || exprp->num().isFourState() || exprp->num().width() != 32) {
                         longname
                             += ("_" + paramSmallName(srcModp, modvarp) + paramValueNumber(exprp));
                         any_overrides = true;

test_regress/t/t_param_width.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;

test_regress/t/t_param_width.v

@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2016 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// issue 1991
+
+module t
+  (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   socket #(3'b000) s0();
+   socket #(3'b010) s1();
+   socket #(2'b10) s2();
+   socket #(2'b11) s3();
+
+   always_ff @ (posedge clk) begin
+      if (s0.ADDR != 0) $stop;
+      if (s1.ADDR != 2) $stop;
+      if (s2.ADDR != 2) $stop;
+      if (s3.ADDR != 3) $stop;
+      if ($bits(s0.ADDR) != 3) $stop;
+      if ($bits(s1.ADDR) != 3) $stop;
+      if ($bits(s2.ADDR) != 2) $stop;
+      if ($bits(s3.ADDR) != 2) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule
+
+module socket #(ADDR)();
+   initial
+     $display("bits %0d, addr %b", $bits(ADDR), ADDR);
+endmodule