diff --git a/Changes b/Changes
index 4ce4d40f5..ad852bf44 100644
--- a/Changes
+++ b/Changes
@@ -13,6 +13,8 @@ Verilator 4.211 devel
 
 **Minor:**
 
+* Fix -G to treat simple integer literals as signed (#3060). [Anikin1610]
+
 
 Verilator 4.210 2021-07-07
 ==========================
diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index d878aa615..4ece401fd 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -267,7 +267,7 @@ AstConst* AstConst::parseParamLiteral(FileLine* fl, const string& literal) {
         char* endp;
         int v = strtol(literal.c_str(), &endp, 0);
         if ((v != 0) && (endp[0] == 0)) {  // C literal
-            return new AstConst(fl, AstConst::WidthedValue(), 32, v);
+            return new AstConst(fl, AstConst::Signed32(), v);
         } else {  // Try a Verilog literal (fatals if not)
             return new AstConst(fl, AstConst::StringToParse(), literal.c_str());
         }
diff --git a/test_regress/t/t_flag_parameter.v b/test_regress/t/t_flag_parameter.v
index 33f1c102e..4fe3ad8ee 100644
--- a/test_regress/t/t_flag_parameter.v
+++ b/test_regress/t/t_flag_parameter.v
@@ -53,6 +53,8 @@ module t;
    parameter int52 = 1;
    parameter int61 = 1;
    parameter int62 = 1;
+   parameter int71 = 1;
+   parameter int72 = 1;
 
    initial begin
       `check(string1,"New String");
@@ -83,6 +85,11 @@ module t;
       `check(int52,32'hdeadbeef);
       `check(int61,32'hdeadbeef);
       `check(int62,32'hdeadbeef);
+      `check(int71,-1000);
+      `check(int72,-1000);
+
+      // Check parameter assigned simple integer literal is signed
+      if ((int11 << 27) >>> 31 != -1) $stop;
 
       $write("*-* All Finished *-*\n");
       $finish;
diff --git a/test_regress/t/t_flag_parameter.vc b/test_regress/t/t_flag_parameter.vc
index 955540440..35687e39e 100644
--- a/test_regress/t/t_flag_parameter.vc
+++ b/test_regress/t/t_flag_parameter.vc
@@ -26,3 +26,5 @@
 -pvalue+int52=32\'hdead_beef
 -Gint61="32'hdead_beef"
 -pvalue+int62="32'hdead_beef"
+-Gint71=-1000
+-pvalue+int72=-1000