forked from github/verilator
Add FST SystemC tracing (#2806)
This commit is contained in:
Àlex Torregrosa
GitHub
parent
961a2fef61
commit
a29ac44af9
@ -5390,8 +5390,19 @@ build time, should you require.
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=item How do I generate FST waveforms (aka dumps or traces) in SystemC?
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The FST library from GTKWave does not currently support SystemC; use VCD
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format instead.
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FST is a trace file format developed by GTKWave. Verilator provides basic FST
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support. To dump traces in FST format, add the --trace-fst switch to Verilator
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and either A. use $dumpfile/$dumpvars in Verilog as described in the FST
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example above, or B. in C++ change the include described in the FST example
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above:
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#include "verilated_fst_sc.h"
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VerilatedFstSc* tfp = new VerilatedFstSc;
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Note that currently supporting both FST and VCD in a single simulation is
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impossible, but such requirement should be rare. You can however ifdef
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around the trace format in your C++ main loop, and select VCD or FST at
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build time, should you require.
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=item How do I view waveforms (aka dumps or traces)?
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@ -128,7 +128,7 @@ template <> void VerilatedTrace<VerilatedFst>::set_time_resolution(const std::st
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/// Create a FST dump file in C standalone (no SystemC) simulations.
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/// Also derived for use in SystemC simulations.
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class VerilatedFstC final {
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class VerilatedFstC VL_NOT_FINAL {
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VerilatedFst m_sptrace; // Trace file being created
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// CONSTRUCTORS
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84
include/verilated_fst_sc.cpp
Normal file
84
include/verilated_fst_sc.cpp
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@ -0,0 +1,84 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//=============================================================================
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//
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// THIS MODULE IS PUBLICLY LICENSED
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//
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// Copyright 2001-2021 by Wilson Snyder. This program is free software; you
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// can redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//=============================================================================
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///
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/// \file
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/// \brief Verilated tracing in FST for SystemC implementation code
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///
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/// This file must be compiled and linked against all Verilated objects
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/// that use --sc --trace-fst.
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///
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/// Use "verilator --sc --trace-fst" to add this to the Makefile for the linker.
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///
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//=============================================================================
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#include "verilatedos.h"
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#include "verilated_fst_sc.h"
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//======================================================================
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//======================================================================
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//--------------------------------------------------
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// SystemC 2.1.v1
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// cppcheck-suppress unusedFunction
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void VerilatedFstSc::write_comment(const std::string&) {}
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void VerilatedFstSc::trace(const unsigned int&, const std::string&, const char**) {}
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#define DECL_TRACE_METHOD_A(tp) \
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void VerilatedFstSc::trace(const tp& object, const std::string& name) {}
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#define DECL_TRACE_METHOD_B(tp) \
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void VerilatedFstSc::trace(const tp& object, const std::string& name, int width) {}
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// clang-format off
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#if (SYSTEMC_VERSION >= 20171012)
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DECL_TRACE_METHOD_A( sc_event )
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DECL_TRACE_METHOD_A( sc_time )
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#endif
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DECL_TRACE_METHOD_A( bool )
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DECL_TRACE_METHOD_A( sc_dt::sc_bit )
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DECL_TRACE_METHOD_A( sc_dt::sc_logic )
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DECL_TRACE_METHOD_B( unsigned char )
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DECL_TRACE_METHOD_B( unsigned short )
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DECL_TRACE_METHOD_B( unsigned int )
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DECL_TRACE_METHOD_B( unsigned long )
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#ifdef SYSTEMC_64BIT_PATCHES
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DECL_TRACE_METHOD_B( unsigned long long)
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#endif
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DECL_TRACE_METHOD_B( char )
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DECL_TRACE_METHOD_B( short )
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DECL_TRACE_METHOD_B( int )
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DECL_TRACE_METHOD_B( long )
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DECL_TRACE_METHOD_B( sc_dt::int64 )
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DECL_TRACE_METHOD_B( sc_dt::uint64 )
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DECL_TRACE_METHOD_A( float )
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DECL_TRACE_METHOD_A( double )
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DECL_TRACE_METHOD_A( sc_dt::sc_int_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_uint_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_signed )
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DECL_TRACE_METHOD_A( sc_dt::sc_unsigned )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxval )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxnum )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast )
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DECL_TRACE_METHOD_A( sc_dt::sc_bv_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_lv_base )
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// clang-format on
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#undef DECL_TRACE_METHOD_A
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#undef DECL_TRACE_METHOD_B
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//********************************************************************
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123
include/verilated_fst_sc.h
Normal file
123
include/verilated_fst_sc.h
Normal file
@ -0,0 +1,123 @@
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// -*- mode: C++; c-file-style: "cc-mode" -*-
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//=============================================================================
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//
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// Copyright 2001-2021 by Wilson Snyder. This program is free software; you can
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// redistribute it and/or modify it under the terms of either the GNU
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// Lesser General Public License Version 3 or the Perl Artistic License
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// Version 2.0.
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// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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//
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//=============================================================================
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///
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/// \file
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/// \brief Verilator tracing in FST format for SystemC header
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///
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/// User wrapper code should use this header when creating FST SystemC
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/// traces.
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///
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/// This class is not threadsafe, as the SystemC kernel is not threadsafe.
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///
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//=============================================================================
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#ifndef _VERILATED_FST_SC_H_
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#define _VERILATED_FST_SC_H_ 1
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#include "verilatedos.h"
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#include "verilated_sc.h"
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#include "verilated_fst_c.h"
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//=============================================================================
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// VerilatedFstSc
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///
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/// This class is passed to the SystemC simulation kernel, just like a
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/// documented SystemC trace format.
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class VerilatedFstSc final : sc_trace_file, public VerilatedFstC {
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// CONSTRUCTORS
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VL_UNCOPYABLE(VerilatedFstSc);
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public:
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VerilatedFstSc() {
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sc_get_curr_simcontext()->add_trace_file(this);
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// We want to avoid a depreciated warning, but still be back compatible.
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// Turning off the message just for this still results in an
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// annoying "to turn off" message.
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sc_time t1sec(1, SC_SEC);
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if (t1sec.to_default_time_units() != 0) {
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sc_time tunits(1.0 / t1sec.to_default_time_units(), SC_SEC);
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spTrace()->set_time_unit(tunits.to_string());
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}
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spTrace()->set_time_resolution(sc_get_time_resolution().to_string());
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}
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virtual ~VerilatedFstSc() { close(); }
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// METHODS
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/// Called by SystemC simulate()
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virtual void cycle(bool delta_cycle) {
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if (!delta_cycle) { this->dump(sc_time_stamp().to_double()); }
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}
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private:
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/// Fake outs for linker
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#ifdef NC_SYSTEMC
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// Cadence Incisive has these as abstract functions so we must create them
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virtual void set_time_unit(int exponent10_seconds) {} // deprecated
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#endif
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virtual void set_time_unit(double v, sc_time_unit tu) {} // LCOV_EXCL_LINE
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//--------------------------------------------------
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// SystemC 2.1.v1
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#define DECL_TRACE_METHOD_A(tp) virtual void trace(const tp& object, const std::string& name);
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#define DECL_TRACE_METHOD_B(tp) \
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virtual void trace(const tp& object, const std::string& name, int width);
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virtual void write_comment(const std::string&);
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virtual void trace(const unsigned int&, const std::string&, const char**);
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// clang-format off
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// Formatting matches that of sc_trace.h
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#if (SYSTEMC_VERSION >= 20171012)
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DECL_TRACE_METHOD_A( sc_event )
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DECL_TRACE_METHOD_A( sc_time )
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#endif
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DECL_TRACE_METHOD_A( bool )
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DECL_TRACE_METHOD_A( sc_dt::sc_bit )
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DECL_TRACE_METHOD_A( sc_dt::sc_logic )
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DECL_TRACE_METHOD_B( unsigned char )
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DECL_TRACE_METHOD_B( unsigned short )
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DECL_TRACE_METHOD_B( unsigned int )
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DECL_TRACE_METHOD_B( unsigned long )
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#ifdef SYSTEMC_64BIT_PATCHES
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DECL_TRACE_METHOD_B( unsigned long long)
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#endif
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DECL_TRACE_METHOD_B( char )
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DECL_TRACE_METHOD_B( short )
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DECL_TRACE_METHOD_B( int )
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DECL_TRACE_METHOD_B( long )
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DECL_TRACE_METHOD_B( sc_dt::int64 )
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DECL_TRACE_METHOD_B( sc_dt::uint64 )
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DECL_TRACE_METHOD_A( float )
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DECL_TRACE_METHOD_A( double )
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DECL_TRACE_METHOD_A( sc_dt::sc_int_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_uint_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_signed )
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DECL_TRACE_METHOD_A( sc_dt::sc_unsigned )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxval )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxval_fast )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxnum )
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DECL_TRACE_METHOD_A( sc_dt::sc_fxnum_fast )
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DECL_TRACE_METHOD_A( sc_dt::sc_bv_base )
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DECL_TRACE_METHOD_A( sc_dt::sc_lv_base )
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// clang-format on
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#undef DECL_TRACE_METHOD_A
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#undef DECL_TRACE_METHOD_B
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};
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#endif // Guard
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@ -108,13 +108,7 @@ public:
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if (v3Global.opt.trace()) {
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putMakeClassEntry(of, v3Global.opt.traceSourceBase() + "_c.cpp");
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if (v3Global.opt.systemC()) {
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if (v3Global.opt.traceFormat() != TraceFormat::VCD) {
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v3warn(E_UNSUPPORTED,
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"Unsupported: This trace format is not supported "
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"in SystemC, use VCD format.");
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} else {
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putMakeClassEntry(of, v3Global.opt.traceSourceLang() + ".cpp");
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}
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putMakeClassEntry(of, v3Global.opt.traceSourceLang() + ".cpp");
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}
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}
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if (v3Global.opt.mtasks()) putMakeClassEntry(of, "verilated_threads.cpp");
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@ -888,7 +888,8 @@ sub compile_vlt_flags {
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$self->{sc} = 1 if ($checkflags =~ /-sc\b/);
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$self->{trace} = ($opt_trace || $checkflags =~ /-trace\b/
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|| $checkflags =~ /-trace-fst\b/);
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$self->{trace_format} = (($checkflags =~ /-trace-fst/ && 'fst-c')
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$self->{trace_format} = (($checkflags =~ /-trace-fst/ && $self->{sc} && 'fst-sc')
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|| ($checkflags =~ /-trace-fst/ && !$self->{sc} && 'fst-c')
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|| ($self->{sc} && 'vcd-sc')
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|| (!$self->{sc} && 'vcd-c'));
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$self->{savable} = 1 if ($checkflags =~ /-savable\b/);
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@ -1747,6 +1748,7 @@ sub _make_main {
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print $fh "#include \"verilated.h\"\n";
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print $fh "#include \"systemc.h\"\n" if $self->sc;
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print $fh "#include \"verilated_fst_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-c';
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print $fh "#include \"verilated_fst_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'fst-sc';
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print $fh "#include \"verilated_vcd_c.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-c';
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print $fh "#include \"verilated_vcd_sc.h\"\n" if $self->{trace} && $self->{trace_format} eq 'vcd-sc';
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print $fh "#include \"verilated_save.h\"\n" if $self->{savable};
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@ -1808,6 +1810,7 @@ sub _make_main {
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$fh->print("#if VM_TRACE\n");
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$fh->print(" contextp->traceEverOn(true);\n");
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$fh->print(" std::unique_ptr<VerilatedFstC> tfp{new VerilatedFstC};\n") if $self->{trace_format} eq 'fst-c';
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$fh->print(" std::unique_ptr<VerilatedFstSc> tfp{new VerilatedFstSc};\n") if $self->{trace_format} eq 'fst-sc';
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$fh->print(" std::unique_ptr<VerilatedVcdC> tfp{new VerilatedVcdC};\n") if $self->{trace_format} eq 'vcd-c';
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$fh->print(" std::unique_ptr<VerilatedVcdSc> tfp{new VerilatedVcdSc};\n") if $self->{trace_format} eq 'vcd-sc';
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$fh->print(" topp->trace(tfp.get(), 99);\n");
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769
test_regress/t/t_interface_ref_trace_fst_sc.out
Normal file
769
test_regress/t/t_interface_ref_trace_fst_sc.out
Normal file
@ -0,0 +1,769 @@
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$date
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Thu Apr 1 14:51:24 2021
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$end
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$version
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fstWriter
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$end
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$timescale
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1ps
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$end
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$scope module top $end
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$scope module t $end
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$var wire 1 ! clk $end
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$var integer 32 " cyc $end
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$scope module intf_1 $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$scope module s1 $end
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$scope module intf_for_struct $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module c1 $end
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$scope module intf_for_check $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module a $end
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$scope module intf_one $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$scope module ac1 $end
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$scope module intf_for_check $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module abcdefghijklmnopqrstuvwxyz $end
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$scope module intf_two $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$scope module ac2 $end
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$scope module intf_for_check $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 # value $end
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$scope module the_struct $end
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$var logic 32 $ val100 $end
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$var logic 32 % val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module intf_2 $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 & value $end
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$scope module the_struct $end
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$var logic 32 ' val100 $end
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$var logic 32 ( val200 $end
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$upscope $end
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$upscope $end
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$scope module s2 $end
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$scope module intf_for_struct $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 & value $end
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$scope module the_struct $end
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$var logic 32 ' val100 $end
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$var logic 32 ( val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module c2 $end
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$scope module intf_for_check $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 & value $end
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$scope module the_struct $end
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$var logic 32 ' val100 $end
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$var logic 32 ( val200 $end
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$upscope $end
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$upscope $end
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$upscope $end
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$scope module a $end
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$scope module intf_two $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 & value $end
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$scope module the_struct $end
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$var logic 32 ' val100 $end
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$var logic 32 ( val200 $end
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$upscope $end
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$upscope $end
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$scope module ac2 $end
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$scope module intf_for_check $end
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$var wire 1 ! clk $end
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$var wire 32 " cyc $end
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$var integer 32 & value $end
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$scope module the_struct $end
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$var logic 32 ' val100 $end
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$var logic 32 ( val200 $end
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$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module abcdefghijklmnopqrstuvwxyz $end
|
||||
$scope module intf_one $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 & value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 ' val100 $end
|
||||
$var logic 32 ( val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module ac1 $end
|
||||
$scope module intf_for_check $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 & value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 ' val100 $end
|
||||
$var logic 32 ( val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module a $end
|
||||
$scope module intf_in_sub_all $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 ) value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 * val100 $end
|
||||
$var logic 32 + val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module as3 $end
|
||||
$scope module intf_for_struct $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 ) value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 * val100 $end
|
||||
$var logic 32 + val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module ac3 $end
|
||||
$scope module intf_for_check $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 ) value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 * val100 $end
|
||||
$var logic 32 + val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module abcdefghijklmnopqrstuvwxyz $end
|
||||
$scope module intf_in_sub_all $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 , value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 - val100 $end
|
||||
$var logic 32 . val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module as3 $end
|
||||
$scope module intf_for_struct $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 , value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 - val100 $end
|
||||
$var logic 32 . val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module ac3 $end
|
||||
$scope module intf_for_check $end
|
||||
$var wire 1 ! clk $end
|
||||
$var wire 32 " cyc $end
|
||||
$var integer 32 , value $end
|
||||
$scope module the_struct $end
|
||||
$var logic 32 - val100 $end
|
||||
$var logic 32 . val200 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b00000000000000000000010010110010 .
|
||||
b00000000000000000000010001001110 -
|
||||
b00000000000000000000001111101010 ,
|
||||
b00000000000000000000010010110001 +
|
||||
b00000000000000000000010001001101 *
|
||||
b00000000000000000000001111101001 )
|
||||
b00000000000000000000000011001010 (
|
||||
b00000000000000000000000001100110 '
|
||||
b00000000000000000000000000000010 &
|
||||
b00000000000000000000000011001001 %
|
||||
b00000000000000000000000001100101 $
|
||||
b00000000000000000000000000000001 #
|
||||
b00000000000000000000000000000000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b00000000000000000000000000000001 "
|
||||
b00000000000000000000000000000010 #
|
||||
b00000000000000000000000001100110 $
|
||||
b00000000000000000000000011001010 %
|
||||
b00000000000000000000000000000011 &
|
||||
b00000000000000000000000001100111 '
|
||||
b00000000000000000000000011001011 (
|
||||
b00000000000000000000001111101010 )
|
||||
b00000000000000000000010001001110 *
|
||||
b00000000000000000000010010110010 +
|
||||
b00000000000000000000001111101011 ,
|
||||
b00000000000000000000010001001111 -
|
||||
b00000000000000000000010010110011 .
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b00000000000000000000010010110100 .
|
||||
b00000000000000000000010001010000 -
|
||||
b00000000000000000000001111101100 ,
|
||||
b00000000000000000000010010110011 +
|
||||
b00000000000000000000010001001111 *
|
||||
b00000000000000000000001111101011 )
|
||||
b00000000000000000000000011001100 (
|
||||
b00000000000000000000000001101000 '
|
||||
b00000000000000000000000000000100 &
|
||||
b00000000000000000000000011001011 %
|
||||
b00000000000000000000000001100111 $
|
||||
b00000000000000000000000000000011 #
|
||||
b00000000000000000000000000000010 "
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b00000000000000000000000000000011 "
|
||||
b00000000000000000000000000000100 #
|
||||
b00000000000000000000000001101000 $
|
||||
b00000000000000000000000011001100 %
|
||||
b00000000000000000000000000000101 &
|
||||
b00000000000000000000000001101001 '
|
||||
b00000000000000000000000011001101 (
|
||||
b00000000000000000000001111101100 )
|
||||
b00000000000000000000010001010000 *
|
||||
b00000000000000000000010010110100 +
|
||||
b00000000000000000000001111101101 ,
|
||||
b00000000000000000000010001010001 -
|
||||
b00000000000000000000010010110101 .
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
b00000000000000000000010010110110 .
|
||||
b00000000000000000000010001010010 -
|
||||
b00000000000000000000001111101110 ,
|
||||
b00000000000000000000010010110101 +
|
||||
b00000000000000000000010001010001 *
|
||||
b00000000000000000000001111101101 )
|
||||
b00000000000000000000000011001110 (
|
||||
b00000000000000000000000001101010 '
|
||||
b00000000000000000000000000000110 &
|
||||
b00000000000000000000000011001101 %
|
||||
b00000000000000000000000001101001 $
|
||||
b00000000000000000000000000000101 #
|
||||
b00000000000000000000000000000100 "
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
#45
|
||||
0!
|
||||
#46
|
||||
#47
|
||||
#48
|
||||
#49
|
||||
#50
|
||||
1!
|
||||
b00000000000000000000000000000101 "
|
||||
b00000000000000000000000000000110 #
|
||||
b00000000000000000000000001101010 $
|
||||
b00000000000000000000000011001110 %
|
||||
b00000000000000000000000000000111 &
|
||||
b00000000000000000000000001101011 '
|
||||
b00000000000000000000000011001111 (
|
||||
b00000000000000000000001111101110 )
|
||||
b00000000000000000000010001010010 *
|
||||
b00000000000000000000010010110110 +
|
||||
b00000000000000000000001111101111 ,
|
||||
b00000000000000000000010001010011 -
|
||||
b00000000000000000000010010110111 .
|
||||
#51
|
||||
#52
|
||||
#53
|
||||
#54
|
||||
#55
|
||||
0!
|
||||
#56
|
||||
#57
|
||||
#58
|
||||
#59
|
||||
#60
|
||||
1!
|
||||
b00000000000000000000010010111000 .
|
||||
b00000000000000000000010001010100 -
|
||||
b00000000000000000000001111110000 ,
|
||||
b00000000000000000000010010110111 +
|
||||
b00000000000000000000010001010011 *
|
||||
b00000000000000000000001111101111 )
|
||||
b00000000000000000000000011010000 (
|
||||
b00000000000000000000000001101100 '
|
||||
b00000000000000000000000000001000 &
|
||||
b00000000000000000000000011001111 %
|
||||
b00000000000000000000000001101011 $
|
||||
b00000000000000000000000000000111 #
|
||||
b00000000000000000000000000000110 "
|
||||
#61
|
||||
#62
|
||||
#63
|
||||
#64
|
||||
#65
|
||||
0!
|
||||
#66
|
||||
#67
|
||||
#68
|
||||
#69
|
||||
#70
|
||||
1!
|
||||
b00000000000000000000000000000111 "
|
||||
b00000000000000000000000000001000 #
|
||||
b00000000000000000000000001101100 $
|
||||
b00000000000000000000000011010000 %
|
||||
b00000000000000000000000000001001 &
|
||||
b00000000000000000000000001101101 '
|
||||
b00000000000000000000000011010001 (
|
||||
b00000000000000000000001111110000 )
|
||||
b00000000000000000000010001010100 *
|
||||
b00000000000000000000010010111000 +
|
||||
b00000000000000000000001111110001 ,
|
||||
b00000000000000000000010001010101 -
|
||||
b00000000000000000000010010111001 .
|
||||
#71
|
||||
#72
|
||||
#73
|
||||
#74
|
||||
#75
|
||||
0!
|
||||
#76
|
||||
#77
|
||||
#78
|
||||
#79
|
||||
#80
|
||||
1!
|
||||
b00000000000000000000010010111010 .
|
||||
b00000000000000000000010001010110 -
|
||||
b00000000000000000000001111110010 ,
|
||||
b00000000000000000000010010111001 +
|
||||
b00000000000000000000010001010101 *
|
||||
b00000000000000000000001111110001 )
|
||||
b00000000000000000000000011010010 (
|
||||
b00000000000000000000000001101110 '
|
||||
b00000000000000000000000000001010 &
|
||||
b00000000000000000000000011010001 %
|
||||
b00000000000000000000000001101101 $
|
||||
b00000000000000000000000000001001 #
|
||||
b00000000000000000000000000001000 "
|
||||
#81
|
||||
#82
|
||||
#83
|
||||
#84
|
||||
#85
|
||||
0!
|
||||
#86
|
||||
#87
|
||||
#88
|
||||
#89
|
||||
#90
|
||||
1!
|
||||
b00000000000000000000000000001001 "
|
||||
b00000000000000000000000000001010 #
|
||||
b00000000000000000000000001101110 $
|
||||
b00000000000000000000000011010010 %
|
||||
b00000000000000000000000000001011 &
|
||||
b00000000000000000000000001101111 '
|
||||
b00000000000000000000000011010011 (
|
||||
b00000000000000000000001111110010 )
|
||||
b00000000000000000000010001010110 *
|
||||
b00000000000000000000010010111010 +
|
||||
b00000000000000000000001111110011 ,
|
||||
b00000000000000000000010001010111 -
|
||||
b00000000000000000000010010111011 .
|
||||
#91
|
||||
#92
|
||||
#93
|
||||
#94
|
||||
#95
|
||||
0!
|
||||
#96
|
||||
#97
|
||||
#98
|
||||
#99
|
||||
#100
|
||||
1!
|
||||
b00000000000000000000010010111100 .
|
||||
b00000000000000000000010001011000 -
|
||||
b00000000000000000000001111110100 ,
|
||||
b00000000000000000000010010111011 +
|
||||
b00000000000000000000010001010111 *
|
||||
b00000000000000000000001111110011 )
|
||||
b00000000000000000000000011010100 (
|
||||
b00000000000000000000000001110000 '
|
||||
b00000000000000000000000000001100 &
|
||||
b00000000000000000000000011010011 %
|
||||
b00000000000000000000000001101111 $
|
||||
b00000000000000000000000000001011 #
|
||||
b00000000000000000000000000001010 "
|
||||
#101
|
||||
#102
|
||||
#103
|
||||
#104
|
||||
#105
|
||||
0!
|
||||
#106
|
||||
#107
|
||||
#108
|
||||
#109
|
||||
#110
|
||||
1!
|
||||
b00000000000000000000000000001011 "
|
||||
b00000000000000000000000000001100 #
|
||||
b00000000000000000000000001110000 $
|
||||
b00000000000000000000000011010100 %
|
||||
b00000000000000000000000000001101 &
|
||||
b00000000000000000000000001110001 '
|
||||
b00000000000000000000000011010101 (
|
||||
b00000000000000000000001111110100 )
|
||||
b00000000000000000000010001011000 *
|
||||
b00000000000000000000010010111100 +
|
||||
b00000000000000000000001111110101 ,
|
||||
b00000000000000000000010001011001 -
|
||||
b00000000000000000000010010111101 .
|
||||
#111
|
||||
#112
|
||||
#113
|
||||
#114
|
||||
#115
|
||||
0!
|
||||
#116
|
||||
#117
|
||||
#118
|
||||
#119
|
||||
#120
|
||||
1!
|
||||
b00000000000000000000010010111110 .
|
||||
b00000000000000000000010001011010 -
|
||||
b00000000000000000000001111110110 ,
|
||||
b00000000000000000000010010111101 +
|
||||
b00000000000000000000010001011001 *
|
||||
b00000000000000000000001111110101 )
|
||||
b00000000000000000000000011010110 (
|
||||
b00000000000000000000000001110010 '
|
||||
b00000000000000000000000000001110 &
|
||||
b00000000000000000000000011010101 %
|
||||
b00000000000000000000000001110001 $
|
||||
b00000000000000000000000000001101 #
|
||||
b00000000000000000000000000001100 "
|
||||
#121
|
||||
#122
|
||||
#123
|
||||
#124
|
||||
#125
|
||||
0!
|
||||
#126
|
||||
#127
|
||||
#128
|
||||
#129
|
||||
#130
|
||||
1!
|
||||
b00000000000000000000000000001101 "
|
||||
b00000000000000000000000000001110 #
|
||||
b00000000000000000000000001110010 $
|
||||
b00000000000000000000000011010110 %
|
||||
b00000000000000000000000000001111 &
|
||||
b00000000000000000000000001110011 '
|
||||
b00000000000000000000000011010111 (
|
||||
b00000000000000000000001111110110 )
|
||||
b00000000000000000000010001011010 *
|
||||
b00000000000000000000010010111110 +
|
||||
b00000000000000000000001111110111 ,
|
||||
b00000000000000000000010001011011 -
|
||||
b00000000000000000000010010111111 .
|
||||
#131
|
||||
#132
|
||||
#133
|
||||
#134
|
||||
#135
|
||||
0!
|
||||
#136
|
||||
#137
|
||||
#138
|
||||
#139
|
||||
#140
|
||||
1!
|
||||
b00000000000000000000010011000000 .
|
||||
b00000000000000000000010001011100 -
|
||||
b00000000000000000000001111111000 ,
|
||||
b00000000000000000000010010111111 +
|
||||
b00000000000000000000010001011011 *
|
||||
b00000000000000000000001111110111 )
|
||||
b00000000000000000000000011011000 (
|
||||
b00000000000000000000000001110100 '
|
||||
b00000000000000000000000000010000 &
|
||||
b00000000000000000000000011010111 %
|
||||
b00000000000000000000000001110011 $
|
||||
b00000000000000000000000000001111 #
|
||||
b00000000000000000000000000001110 "
|
||||
#141
|
||||
#142
|
||||
#143
|
||||
#144
|
||||
#145
|
||||
0!
|
||||
#146
|
||||
#147
|
||||
#148
|
||||
#149
|
||||
#150
|
||||
1!
|
||||
b00000000000000000000000000001111 "
|
||||
b00000000000000000000000000010000 #
|
||||
b00000000000000000000000001110100 $
|
||||
b00000000000000000000000011011000 %
|
||||
b00000000000000000000000000010001 &
|
||||
b00000000000000000000000001110101 '
|
||||
b00000000000000000000000011011001 (
|
||||
b00000000000000000000001111111000 )
|
||||
b00000000000000000000010001011100 *
|
||||
b00000000000000000000010011000000 +
|
||||
b00000000000000000000001111111001 ,
|
||||
b00000000000000000000010001011101 -
|
||||
b00000000000000000000010011000001 .
|
||||
#151
|
||||
#152
|
||||
#153
|
||||
#154
|
||||
#155
|
||||
0!
|
||||
#156
|
||||
#157
|
||||
#158
|
||||
#159
|
||||
#160
|
||||
1!
|
||||
b00000000000000000000010011000010 .
|
||||
b00000000000000000000010001011110 -
|
||||
b00000000000000000000001111111010 ,
|
||||
b00000000000000000000010011000001 +
|
||||
b00000000000000000000010001011101 *
|
||||
b00000000000000000000001111111001 )
|
||||
b00000000000000000000000011011010 (
|
||||
b00000000000000000000000001110110 '
|
||||
b00000000000000000000000000010010 &
|
||||
b00000000000000000000000011011001 %
|
||||
b00000000000000000000000001110101 $
|
||||
b00000000000000000000000000010001 #
|
||||
b00000000000000000000000000010000 "
|
||||
#161
|
||||
#162
|
||||
#163
|
||||
#164
|
||||
#165
|
||||
0!
|
||||
#166
|
||||
#167
|
||||
#168
|
||||
#169
|
||||
#170
|
||||
1!
|
||||
b00000000000000000000000000010001 "
|
||||
b00000000000000000000000000010010 #
|
||||
b00000000000000000000000001110110 $
|
||||
b00000000000000000000000011011010 %
|
||||
b00000000000000000000000000010011 &
|
||||
b00000000000000000000000001110111 '
|
||||
b00000000000000000000000011011011 (
|
||||
b00000000000000000000001111111010 )
|
||||
b00000000000000000000010001011110 *
|
||||
b00000000000000000000010011000010 +
|
||||
b00000000000000000000001111111011 ,
|
||||
b00000000000000000000010001011111 -
|
||||
b00000000000000000000010011000011 .
|
||||
#171
|
||||
#172
|
||||
#173
|
||||
#174
|
||||
#175
|
||||
0!
|
||||
#176
|
||||
#177
|
||||
#178
|
||||
#179
|
||||
#180
|
||||
1!
|
||||
b00000000000000000000010011000100 .
|
||||
b00000000000000000000010001100000 -
|
||||
b00000000000000000000001111111100 ,
|
||||
b00000000000000000000010011000011 +
|
||||
b00000000000000000000010001011111 *
|
||||
b00000000000000000000001111111011 )
|
||||
b00000000000000000000000011011100 (
|
||||
b00000000000000000000000001111000 '
|
||||
b00000000000000000000000000010100 &
|
||||
b00000000000000000000000011011011 %
|
||||
b00000000000000000000000001110111 $
|
||||
b00000000000000000000000000010011 #
|
||||
b00000000000000000000000000010010 "
|
||||
#181
|
||||
#182
|
||||
#183
|
||||
#184
|
||||
#185
|
||||
0!
|
||||
#186
|
||||
#187
|
||||
#188
|
||||
#189
|
||||
#190
|
||||
1!
|
||||
b00000000000000000000000000010011 "
|
||||
b00000000000000000000000000010100 #
|
||||
b00000000000000000000000001111000 $
|
||||
b00000000000000000000000011011100 %
|
||||
b00000000000000000000000000010101 &
|
||||
b00000000000000000000000001111001 '
|
||||
b00000000000000000000000011011101 (
|
||||
b00000000000000000000001111111100 )
|
||||
b00000000000000000000010001100000 *
|
||||
b00000000000000000000010011000100 +
|
||||
b00000000000000000000001111111101 ,
|
||||
b00000000000000000000010001100001 -
|
||||
b00000000000000000000010011000101 .
|
||||
#191
|
||||
#192
|
||||
#193
|
||||
#194
|
||||
#195
|
||||
0!
|
||||
#196
|
||||
#197
|
||||
#198
|
||||
#199
|
||||
#200
|
||||
1!
|
||||
b00000000000000000000010011000110 .
|
||||
b00000000000000000000010001100010 -
|
||||
b00000000000000000000001111111110 ,
|
||||
b00000000000000000000010011000101 +
|
||||
b00000000000000000000010001100001 *
|
||||
b00000000000000000000001111111101 )
|
||||
b00000000000000000000000011011110 (
|
||||
b00000000000000000000000001111010 '
|
||||
b00000000000000000000000000010110 &
|
||||
b00000000000000000000000011011101 %
|
||||
b00000000000000000000000001111001 $
|
||||
b00000000000000000000000000010101 #
|
||||
b00000000000000000000000000010100 "
|
||||
#201
|
||||
#202
|
||||
#203
|
||||
#204
|
||||
#205
|
||||
0!
|
||||
#206
|
||||
#207
|
||||
#208
|
||||
#209
|
||||
#210
|
||||
1!
|
||||
b00000000000000000000000000010101 "
|
||||
b00000000000000000000000000010110 #
|
||||
b00000000000000000000000001111010 $
|
||||
b00000000000000000000000011011110 %
|
||||
b00000000000000000000000000010111 &
|
||||
b00000000000000000000000001111011 '
|
||||
b00000000000000000000000011011111 (
|
||||
b00000000000000000000001111111110 )
|
||||
b00000000000000000000010001100010 *
|
||||
b00000000000000000000010011000110 +
|
||||
b00000000000000000000001111111111 ,
|
||||
b00000000000000000000010001100011 -
|
||||
b00000000000000000000010011000111 .
|
||||
#211
|
||||
#212
|
||||
#213
|
||||
#214
|
||||
29
test_regress/t/t_interface_ref_trace_fst_sc.pl
Executable file
29
test_regress/t/t_interface_ref_trace_fst_sc.pl
Executable file
@ -0,0 +1,29 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_interface_ref_trace.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--trace-structs --trace-fst --sc'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
ok(1);
|
||||
1;
|
||||
113
test_regress/t/t_trace_abort_fst_sc.out
Normal file
113
test_regress/t/t_trace_abort_fst_sc.out
Normal file
@ -0,0 +1,113 @@
|
||||
$date
|
||||
Thu Apr 1 14:55:09 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var wire 1 ! clk $end
|
||||
$var logic 3 " cyc $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b001 "
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b010 "
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b011 "
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
b100 "
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
#45
|
||||
0!
|
||||
#46
|
||||
#47
|
||||
#48
|
||||
#49
|
||||
#50
|
||||
1!
|
||||
b101 "
|
||||
#51
|
||||
#52
|
||||
#53
|
||||
#54
|
||||
#55
|
||||
0!
|
||||
#56
|
||||
#57
|
||||
#58
|
||||
#59
|
||||
#60
|
||||
1!
|
||||
b110 "
|
||||
#61
|
||||
#62
|
||||
#63
|
||||
#64
|
||||
#65
|
||||
0!
|
||||
#66
|
||||
#67
|
||||
#68
|
||||
#69
|
||||
#70
|
||||
1!
|
||||
b111 "
|
||||
#71
|
||||
#72
|
||||
#73
|
||||
#74
|
||||
#75
|
||||
0!
|
||||
#76
|
||||
#77
|
||||
#78
|
||||
#79
|
||||
29
test_regress/t/t_trace_abort_fst_sc.pl
Executable file
29
test_regress/t/t_trace_abort_fst_sc.pl
Executable file
@ -0,0 +1,29 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2020 by Geza Lore. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt_all => 1);
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_abort.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst'],
|
||||
);
|
||||
|
||||
execute(
|
||||
fails => 1,
|
||||
);
|
||||
|
||||
fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename});
|
||||
}
|
||||
ok(1);
|
||||
1;
|
||||
33
test_regress/t/t_trace_array_fst_portable_sc.pl
Executable file
33
test_regress/t/t_trace_array_fst_portable_sc.pl
Executable file
@ -0,0 +1,33 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_array.v");
|
||||
golden_filename("t/t_trace_array_fst_sc.out");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-structs',
|
||||
'-CFLAGS -DVL_PORTABLE_ONLY'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
104
test_regress/t/t_trace_array_fst_sc.out
Normal file
104
test_regress/t/t_trace_array_fst_sc.out
Normal file
File diff suppressed because one or more lines are too long
31
test_regress/t/t_trace_array_fst_sc.pl
Executable file
31
test_regress/t/t_trace_array_fst_sc.pl
Executable file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_array.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-structs'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
32
test_regress/t/t_trace_array_fst_threads_1_sc.pl
Executable file
32
test_regress/t/t_trace_array_fst_threads_1_sc.pl
Executable file
@ -0,0 +1,32 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_array.v");
|
||||
golden_filename("t/t_trace_array_fst_sc.out");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-threads 1 --trace-structs'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
32
test_regress/t/t_trace_array_fst_threads_2_sc.pl
Executable file
32
test_regress/t/t_trace_array_fst_threads_2_sc.pl
Executable file
@ -0,0 +1,32 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(vlt => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_array.v");
|
||||
golden_filename("t/t_trace_array_fst_sc.out");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-threads 2 --trace-structs'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
284
test_regress/t/t_trace_complex_fst_sc.out
Normal file
284
test_regress/t/t_trace_complex_fst_sc.out
Normal file
@ -0,0 +1,284 @@
|
||||
$date
|
||||
Thu Apr 1 15:12:03 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var wire 1 ! clk $end
|
||||
$var integer 32 " cyc $end
|
||||
$var logic 2 # v_strp $end
|
||||
$var logic 4 $ v_strp_strp $end
|
||||
$var logic 2 % v_unip_strp $end
|
||||
$var logic 2 & v_arrp $end
|
||||
$var logic 4 ' v_arrp_arrp $end
|
||||
$var logic 4 ( v_arrp_strp $end
|
||||
$var logic 1 ) v_arru(1) $end
|
||||
$var logic 1 * v_arru(2) $end
|
||||
$var logic 1 + v_arru_arru(3)(1) $end
|
||||
$var logic 1 , v_arru_arru(3)(2) $end
|
||||
$var logic 1 - v_arru_arru(4)(1) $end
|
||||
$var logic 1 . v_arru_arru(4)(2) $end
|
||||
$var logic 2 / v_arru_arrp(3) $end
|
||||
$var logic 2 0 v_arru_arrp(4) $end
|
||||
$var logic 2 1 v_arru_strp(3) $end
|
||||
$var logic 2 2 v_arru_strp(4) $end
|
||||
$var real 64 3 v_real $end
|
||||
$var real 64 4 v_arr_real(0) $end
|
||||
$var real 64 5 v_arr_real(1) $end
|
||||
$var logic 64 6 v_str32x2 $end
|
||||
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 7 v_enumed $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 8 v_enumed2 $end
|
||||
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 9 v_enumb $end
|
||||
$var logic 6 : v_enumb2_str $end
|
||||
$var logic 8 ; unpacked_array(-2) $end
|
||||
$var logic 8 < unpacked_array(-1) $end
|
||||
$var logic 8 = unpacked_array(0) $end
|
||||
$var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var integer 32 ? b $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var integer 32 @ a $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module p2 $end
|
||||
$var parameter 32 A PARAM $end
|
||||
$upscope $end
|
||||
$scope module p3 $end
|
||||
$var parameter 32 B PARAM $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module $unit $end
|
||||
$var bit 1 C global_bit $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1C
|
||||
b00000000000000000000000000000011 B
|
||||
b00000000000000000000000000000010 A
|
||||
b00000000000000000000000000000000 @
|
||||
b00000000000000000000000000000000 ?
|
||||
0>
|
||||
b00000000 =
|
||||
b00000000 <
|
||||
b00000000 ;
|
||||
b000000 :
|
||||
b000 9
|
||||
b00000000000000000000000000000000 8
|
||||
b00000000000000000000000000000000 7
|
||||
b0000000000000000000000000000000000000000000000000000000011111111 6
|
||||
r0 5
|
||||
r0 4
|
||||
r0 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
0.
|
||||
0-
|
||||
0,
|
||||
0+
|
||||
0*
|
||||
0)
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b00000000000000000000000000000001 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.1 3
|
||||
r0.2 4
|
||||
r0.3 5
|
||||
b0000000000000000000000000000000100000000000000000000000011111110 6
|
||||
b00000000000000000000000000000001 7
|
||||
b00000000000000000000000000000010 8
|
||||
b111 9
|
||||
b00000000000000000000000000000101 ?
|
||||
b00000000000000000000000000000101 @
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b110 9
|
||||
b00000000000000000000000000000100 8
|
||||
b00000000000000000000000000000010 7
|
||||
b0000000000000000000000000000001000000000000000000000000011111101 6
|
||||
r0.6 5
|
||||
r0.4 4
|
||||
r0.2 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000010 "
|
||||
b111111 :
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b110110 :
|
||||
b00000000000000000000000000000011 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.3 3
|
||||
r0.6000000000000001 4
|
||||
r0.8999999999999999 5
|
||||
b0000000000000000000000000000001100000000000000000000000011111100 6
|
||||
b00000000000000000000000000000011 7
|
||||
b00000000000000000000000000000110 8
|
||||
b101 9
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
b100 9
|
||||
b00000000000000000000000000001000 8
|
||||
b00000000000000000000000000000100 7
|
||||
b0000000000000000000000000000010000000000000000000000000011111011 6
|
||||
r1.2 5
|
||||
r0.8 4
|
||||
r0.4 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000100 "
|
||||
b101101 :
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
#45
|
||||
0!
|
||||
#46
|
||||
#47
|
||||
#48
|
||||
#49
|
||||
#50
|
||||
1!
|
||||
b100100 :
|
||||
b00000000000000000000000000000101 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.5 3
|
||||
r1 4
|
||||
r1.5 5
|
||||
b0000000000000000000000000000010100000000000000000000000011111010 6
|
||||
b00000000000000000000000000000101 7
|
||||
b00000000000000000000000000001010 8
|
||||
b011 9
|
||||
#51
|
||||
#52
|
||||
#53
|
||||
#54
|
||||
#55
|
||||
0!
|
||||
#56
|
||||
#57
|
||||
#58
|
||||
#59
|
||||
#60
|
||||
1!
|
||||
b010 9
|
||||
b00000000000000000000000000001100 8
|
||||
b00000000000000000000000000000110 7
|
||||
b0000000000000000000000000000011000000000000000000000000011111001 6
|
||||
r1.8 5
|
||||
r1.2 4
|
||||
r0.6 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000110 "
|
||||
b011011 :
|
||||
#61
|
||||
#62
|
||||
#63
|
||||
#64
|
||||
31
test_regress/t/t_trace_complex_fst_sc.pl
Executable file
31
test_regress/t/t_trace_complex_fst_sc.pl
Executable file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_complex.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
32
test_regress/t/t_trace_complex_fst_threads_1_sc.pl
Executable file
32
test_regress/t/t_trace_complex_fst_threads_1_sc.pl
Executable file
@ -0,0 +1,32 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_complex.v");
|
||||
golden_filename("t/t_trace_complex_fst_sc.out");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-threads 1'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
32
test_regress/t/t_trace_complex_fst_threads_2_sc.pl
Executable file
32
test_regress/t/t_trace_complex_fst_threads_2_sc.pl
Executable file
@ -0,0 +1,32 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_complex.v");
|
||||
golden_filename("t/t_trace_complex_fst_sc.out");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-threads 2'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
284
test_regress/t/t_trace_complex_params_fst_sc.out
Normal file
284
test_regress/t/t_trace_complex_params_fst_sc.out
Normal file
@ -0,0 +1,284 @@
|
||||
$date
|
||||
Thu Apr 1 15:17:39 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var wire 1 ! clk $end
|
||||
$var integer 32 " cyc $end
|
||||
$var logic 2 # v_strp $end
|
||||
$var logic 4 $ v_strp_strp $end
|
||||
$var logic 2 % v_unip_strp $end
|
||||
$var logic 2 & v_arrp $end
|
||||
$var logic 4 ' v_arrp_arrp $end
|
||||
$var logic 4 ( v_arrp_strp $end
|
||||
$var logic 1 ) v_arru(1) $end
|
||||
$var logic 1 * v_arru(2) $end
|
||||
$var logic 1 + v_arru_arru(3)(1) $end
|
||||
$var logic 1 , v_arru_arru(3)(2) $end
|
||||
$var logic 1 - v_arru_arru(4)(1) $end
|
||||
$var logic 1 . v_arru_arru(4)(2) $end
|
||||
$var logic 2 / v_arru_arrp(3) $end
|
||||
$var logic 2 0 v_arru_arrp(4) $end
|
||||
$var logic 2 1 v_arru_strp(3) $end
|
||||
$var logic 2 2 v_arru_strp(4) $end
|
||||
$var real 64 3 v_real $end
|
||||
$var real 64 4 v_arr_real(0) $end
|
||||
$var real 64 5 v_arr_real(1) $end
|
||||
$var logic 64 6 v_str32x2 $end
|
||||
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 7 v_enumed $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 8 v_enumed2 $end
|
||||
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 9 v_enumb $end
|
||||
$var logic 6 : v_enumb2_str $end
|
||||
$var logic 8 ; unpacked_array(-2) $end
|
||||
$var logic 8 < unpacked_array(-1) $end
|
||||
$var logic 8 = unpacked_array(0) $end
|
||||
$var bit 1 > LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var integer 32 ? b $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var integer 32 @ a $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module p2 $end
|
||||
$var parameter 32 A PARAM $end
|
||||
$upscope $end
|
||||
$scope module p3 $end
|
||||
$var parameter 32 B PARAM $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module $unit $end
|
||||
$var bit 1 C global_bit $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1C
|
||||
b00000000000000000000000000000011 B
|
||||
b00000000000000000000000000000010 A
|
||||
b00000000000000000000000000000000 @
|
||||
b00000000000000000000000000000000 ?
|
||||
0>
|
||||
b00000000 =
|
||||
b00000000 <
|
||||
b00000000 ;
|
||||
b000000 :
|
||||
b000 9
|
||||
b00000000000000000000000000000000 8
|
||||
b00000000000000000000000000000000 7
|
||||
b0000000000000000000000000000000000000000000000000000000011111111 6
|
||||
r0 5
|
||||
r0 4
|
||||
r0 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
0.
|
||||
0-
|
||||
0,
|
||||
0+
|
||||
0*
|
||||
0)
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b00000000000000000000000000000001 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.1 3
|
||||
r0.2 4
|
||||
r0.3 5
|
||||
b0000000000000000000000000000000100000000000000000000000011111110 6
|
||||
b00000000000000000000000000000001 7
|
||||
b00000000000000000000000000000010 8
|
||||
b111 9
|
||||
b00000000000000000000000000000101 ?
|
||||
b00000000000000000000000000000101 @
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b110 9
|
||||
b00000000000000000000000000000100 8
|
||||
b00000000000000000000000000000010 7
|
||||
b0000000000000000000000000000001000000000000000000000000011111101 6
|
||||
r0.6 5
|
||||
r0.4 4
|
||||
r0.2 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000010 "
|
||||
b111111 :
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b110110 :
|
||||
b00000000000000000000000000000011 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.3 3
|
||||
r0.6000000000000001 4
|
||||
r0.8999999999999999 5
|
||||
b0000000000000000000000000000001100000000000000000000000011111100 6
|
||||
b00000000000000000000000000000011 7
|
||||
b00000000000000000000000000000110 8
|
||||
b101 9
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
b100 9
|
||||
b00000000000000000000000000001000 8
|
||||
b00000000000000000000000000000100 7
|
||||
b0000000000000000000000000000010000000000000000000000000011111011 6
|
||||
r1.2 5
|
||||
r0.8 4
|
||||
r0.4 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000100 "
|
||||
b101101 :
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
#45
|
||||
0!
|
||||
#46
|
||||
#47
|
||||
#48
|
||||
#49
|
||||
#50
|
||||
1!
|
||||
b100100 :
|
||||
b00000000000000000000000000000101 "
|
||||
b11 #
|
||||
b1111 $
|
||||
b11 %
|
||||
b11 &
|
||||
b1111 '
|
||||
b1111 (
|
||||
b11 /
|
||||
b11 0
|
||||
b11 1
|
||||
b11 2
|
||||
r0.5 3
|
||||
r1 4
|
||||
r1.5 5
|
||||
b0000000000000000000000000000010100000000000000000000000011111010 6
|
||||
b00000000000000000000000000000101 7
|
||||
b00000000000000000000000000001010 8
|
||||
b011 9
|
||||
#51
|
||||
#52
|
||||
#53
|
||||
#54
|
||||
#55
|
||||
0!
|
||||
#56
|
||||
#57
|
||||
#58
|
||||
#59
|
||||
#60
|
||||
1!
|
||||
b010 9
|
||||
b00000000000000000000000000001100 8
|
||||
b00000000000000000000000000000110 7
|
||||
b0000000000000000000000000000011000000000000000000000000011111001 6
|
||||
r1.8 5
|
||||
r1.2 4
|
||||
r0.6 3
|
||||
b00 2
|
||||
b00 1
|
||||
b00 0
|
||||
b00 /
|
||||
b0000 (
|
||||
b0000 '
|
||||
b00 &
|
||||
b00 %
|
||||
b0000 $
|
||||
b00 #
|
||||
b00000000000000000000000000000110 "
|
||||
b011011 :
|
||||
#61
|
||||
#62
|
||||
#63
|
||||
#64
|
||||
31
test_regress/t/t_trace_complex_params_fst_sc.pl
Executable file
31
test_regress/t/t_trace_complex_params_fst_sc.pl
Executable file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_complex.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --no-trace-structs --trace-params'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
411
test_regress/t/t_trace_complex_structs_fst_sc.out
Normal file
411
test_regress/t/t_trace_complex_structs_fst_sc.out
Normal file
@ -0,0 +1,411 @@
|
||||
$date
|
||||
Thu Apr 1 15:22:14 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var wire 1 ! clk $end
|
||||
$var integer 32 " cyc $end
|
||||
$scope module v_strp $end
|
||||
$var logic 1 # b1 $end
|
||||
$var logic 1 $ b0 $end
|
||||
$upscope $end
|
||||
$scope module v_strp_strp $end
|
||||
$scope module x1 $end
|
||||
$var logic 1 % b1 $end
|
||||
$var logic 1 & b0 $end
|
||||
$upscope $end
|
||||
$scope module x0 $end
|
||||
$var logic 1 ' b1 $end
|
||||
$var logic 1 ( b0 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module v_unip_strp $end
|
||||
$scope module x1 $end
|
||||
$var logic 1 ) b1 $end
|
||||
$var logic 1 * b0 $end
|
||||
$upscope $end
|
||||
$scope module x0 $end
|
||||
$var logic 1 ) b1 $end
|
||||
$var logic 1 * b0 $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$var logic 2 + v_arrp $end
|
||||
$var logic 2 , v_arrp_arrp(3) $end
|
||||
$var logic 2 - v_arrp_arrp(4) $end
|
||||
$scope module v_arrp_strp(3) $end
|
||||
$var logic 1 . b1 $end
|
||||
$var logic 1 / b0 $end
|
||||
$upscope $end
|
||||
$scope module v_arrp_strp(4) $end
|
||||
$var logic 1 0 b1 $end
|
||||
$var logic 1 1 b0 $end
|
||||
$upscope $end
|
||||
$var logic 1 2 v_arru(1) $end
|
||||
$var logic 1 3 v_arru(2) $end
|
||||
$var logic 1 4 v_arru_arru(3)(1) $end
|
||||
$var logic 1 5 v_arru_arru(3)(2) $end
|
||||
$var logic 1 6 v_arru_arru(4)(1) $end
|
||||
$var logic 1 7 v_arru_arru(4)(2) $end
|
||||
$var logic 2 8 v_arru_arrp(3) $end
|
||||
$var logic 2 9 v_arru_arrp(4) $end
|
||||
$scope module v_arru_strp(3) $end
|
||||
$var logic 1 : b1 $end
|
||||
$var logic 1 ; b0 $end
|
||||
$upscope $end
|
||||
$scope module v_arru_strp(4) $end
|
||||
$var logic 1 < b1 $end
|
||||
$var logic 1 = b0 $end
|
||||
$upscope $end
|
||||
$var real 64 > v_real $end
|
||||
$var real 64 ? v_arr_real(0) $end
|
||||
$var real 64 @ v_arr_real(1) $end
|
||||
$scope module v_str32x2(0) $end
|
||||
$var logic 32 A data $end
|
||||
$upscope $end
|
||||
$scope module v_str32x2(1) $end
|
||||
$var logic 32 B data $end
|
||||
$attrbegin misc 07 t.enumed_t 4 ZERO ONE TWO THREE 00000000000000000000000000000000 00000000000000000000000000000001 00000000000000000000000000000010 00000000000000000000000000000011 1 $end
|
||||
$upscope $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 C v_enumed $end
|
||||
$attrbegin misc 07 "" 1 $end
|
||||
$var logic 32 D v_enumed2 $end
|
||||
$attrbegin misc 07 t.enumb_t 4 BZERO BONE BTWO BTHREE 000 001 010 011 2 $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 E v_enumb $end
|
||||
$scope module v_enumb2_str $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 F a $end
|
||||
$attrbegin misc 07 "" 2 $end
|
||||
$var logic 3 G b $end
|
||||
$upscope $end
|
||||
$var logic 8 H unpacked_array(-2) $end
|
||||
$var logic 8 I unpacked_array(-1) $end
|
||||
$var logic 8 J unpacked_array(0) $end
|
||||
$var bit 1 K LONGSTART_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_a_very_long_name_which_will_get_hashed_LONGEND $end
|
||||
$scope module unnamedblk1 $end
|
||||
$var integer 32 L b $end
|
||||
$scope module unnamedblk2 $end
|
||||
$var integer 32 M a $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$scope module $unit $end
|
||||
$var bit 1 N global_bit $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
1N
|
||||
b00000000000000000000000000000000 M
|
||||
b00000000000000000000000000000000 L
|
||||
0K
|
||||
b00000000 J
|
||||
b00000000 I
|
||||
b00000000 H
|
||||
b000 G
|
||||
b000 F
|
||||
b000 E
|
||||
b00000000000000000000000000000000 D
|
||||
b00000000000000000000000000000000 C
|
||||
b00000000000000000000000000000000 B
|
||||
b00000000000000000000000011111111 A
|
||||
r0 @
|
||||
r0 ?
|
||||
r0 >
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
0:
|
||||
b00 9
|
||||
b00 8
|
||||
07
|
||||
06
|
||||
05
|
||||
04
|
||||
03
|
||||
02
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b00 -
|
||||
b00 ,
|
||||
b00 +
|
||||
0*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
b00000000000000000000000000000000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b00000000000000000000000000000001 "
|
||||
1#
|
||||
1$
|
||||
1%
|
||||
1&
|
||||
1'
|
||||
1(
|
||||
1)
|
||||
1*
|
||||
b11 +
|
||||
b11 ,
|
||||
b11 -
|
||||
1.
|
||||
1/
|
||||
10
|
||||
11
|
||||
b11 8
|
||||
b11 9
|
||||
1:
|
||||
1;
|
||||
1<
|
||||
1=
|
||||
r0.1 >
|
||||
r0.2 ?
|
||||
r0.3 @
|
||||
b00000000000000000000000011111110 A
|
||||
b00000000000000000000000000000001 B
|
||||
b00000000000000000000000000000001 C
|
||||
b00000000000000000000000000000010 D
|
||||
b111 E
|
||||
b00000000000000000000000000000101 L
|
||||
b00000000000000000000000000000101 M
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b110 E
|
||||
b00000000000000000000000000000100 D
|
||||
b00000000000000000000000000000010 C
|
||||
b00000000000000000000000000000010 B
|
||||
b00000000000000000000000011111101 A
|
||||
r0.6 @
|
||||
r0.4 ?
|
||||
r0.2 >
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
0:
|
||||
b00 9
|
||||
b00 8
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b00 -
|
||||
b00 ,
|
||||
b00 +
|
||||
0*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
b00000000000000000000000000000010 "
|
||||
b111 F
|
||||
b111 G
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b110 G
|
||||
b110 F
|
||||
b00000000000000000000000000000011 "
|
||||
1#
|
||||
1$
|
||||
1%
|
||||
1&
|
||||
1'
|
||||
1(
|
||||
1)
|
||||
1*
|
||||
b11 +
|
||||
b11 ,
|
||||
b11 -
|
||||
1.
|
||||
1/
|
||||
10
|
||||
11
|
||||
b11 8
|
||||
b11 9
|
||||
1:
|
||||
1;
|
||||
1<
|
||||
1=
|
||||
r0.3 >
|
||||
r0.6000000000000001 ?
|
||||
r0.8999999999999999 @
|
||||
b00000000000000000000000011111100 A
|
||||
b00000000000000000000000000000011 B
|
||||
b00000000000000000000000000000011 C
|
||||
b00000000000000000000000000000110 D
|
||||
b101 E
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
b100 E
|
||||
b00000000000000000000000000001000 D
|
||||
b00000000000000000000000000000100 C
|
||||
b00000000000000000000000000000100 B
|
||||
b00000000000000000000000011111011 A
|
||||
r1.2 @
|
||||
r0.8 ?
|
||||
r0.4 >
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
0:
|
||||
b00 9
|
||||
b00 8
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b00 -
|
||||
b00 ,
|
||||
b00 +
|
||||
0*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
b00000000000000000000000000000100 "
|
||||
b101 F
|
||||
b101 G
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
#45
|
||||
0!
|
||||
#46
|
||||
#47
|
||||
#48
|
||||
#49
|
||||
#50
|
||||
1!
|
||||
b100 G
|
||||
b100 F
|
||||
b00000000000000000000000000000101 "
|
||||
1#
|
||||
1$
|
||||
1%
|
||||
1&
|
||||
1'
|
||||
1(
|
||||
1)
|
||||
1*
|
||||
b11 +
|
||||
b11 ,
|
||||
b11 -
|
||||
1.
|
||||
1/
|
||||
10
|
||||
11
|
||||
b11 8
|
||||
b11 9
|
||||
1:
|
||||
1;
|
||||
1<
|
||||
1=
|
||||
r0.5 >
|
||||
r1 ?
|
||||
r1.5 @
|
||||
b00000000000000000000000011111010 A
|
||||
b00000000000000000000000000000101 B
|
||||
b00000000000000000000000000000101 C
|
||||
b00000000000000000000000000001010 D
|
||||
b011 E
|
||||
#51
|
||||
#52
|
||||
#53
|
||||
#54
|
||||
#55
|
||||
0!
|
||||
#56
|
||||
#57
|
||||
#58
|
||||
#59
|
||||
#60
|
||||
1!
|
||||
b010 E
|
||||
b00000000000000000000000000001100 D
|
||||
b00000000000000000000000000000110 C
|
||||
b00000000000000000000000000000110 B
|
||||
b00000000000000000000000011111001 A
|
||||
r1.8 @
|
||||
r1.2 ?
|
||||
r0.6 >
|
||||
0=
|
||||
0<
|
||||
0;
|
||||
0:
|
||||
b00 9
|
||||
b00 8
|
||||
01
|
||||
00
|
||||
0/
|
||||
0.
|
||||
b00 -
|
||||
b00 ,
|
||||
b00 +
|
||||
0*
|
||||
0)
|
||||
0(
|
||||
0'
|
||||
0&
|
||||
0%
|
||||
0$
|
||||
0#
|
||||
b00000000000000000000000000000110 "
|
||||
b011 F
|
||||
b011 G
|
||||
#61
|
||||
#62
|
||||
#63
|
||||
#64
|
||||
31
test_regress/t/t_trace_complex_structs_fst_sc.pl
Executable file
31
test_regress/t/t_trace_complex_structs_fst_sc.pl
Executable file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_complex.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-structs --no-trace-params'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
1824
test_regress/t/t_trace_fst_sc.out
Normal file
1824
test_regress/t/t_trace_fst_sc.out
Normal file
File diff suppressed because it is too large
Load Diff
30
test_regress/t/t_trace_fst_sc.pl
Executable file
30
test_regress/t/t_trace_fst_sc.pl
Executable file
@ -0,0 +1,30 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2020 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
|
||||
scenarios(vlt_all => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
compile(
|
||||
verilator_flags2 => ["--trace-fst --sc"],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
ok(1);
|
||||
1;
|
||||
98
test_regress/t/t_trace_fst_sc.v
Normal file
98
test_regress/t/t_trace_fst_sc.v
Normal file
@ -0,0 +1,98 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// Author: Yu-Sheng Lin johnjohnlys@media.ee.ntu.edu.tw
|
||||
// SPDX-License-Identifier: CC0-1.0
|
||||
|
||||
module t (/*AUTOARG*/
|
||||
// Inputs
|
||||
clk
|
||||
);
|
||||
|
||||
input clk;
|
||||
|
||||
int cyc;
|
||||
reg rstn;
|
||||
|
||||
parameter real fst_gparam_real = 1.23;
|
||||
localparam real fst_lparam_real = 4.56;
|
||||
real fst_real = 1.23;
|
||||
integer fst_integer;
|
||||
bit fst_bit;
|
||||
logic fst_logic;
|
||||
int fst_int;
|
||||
shortint fst_shortint;
|
||||
longint fst_longint;
|
||||
byte fst_byte;
|
||||
|
||||
parameter fst_parameter = 123;
|
||||
localparam fst_lparam = 456;
|
||||
supply0 fst_supply0;
|
||||
supply1 fst_supply1;
|
||||
tri0 fst_tri0;
|
||||
tri1 fst_tri1;
|
||||
tri fst_tri;
|
||||
wire fst_wire;
|
||||
|
||||
logic [4:0] state;
|
||||
|
||||
Test test (/*AUTOINST*/
|
||||
// Outputs
|
||||
.state (state[4:0]),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.rstn (rstn));
|
||||
|
||||
// Test loop
|
||||
always @ (posedge clk) begin
|
||||
cyc <= cyc + 1;
|
||||
if (cyc==0) begin
|
||||
// Setup
|
||||
rstn <= ~'1;
|
||||
end
|
||||
else if (cyc<10) begin
|
||||
rstn <= ~'1;
|
||||
end
|
||||
else if (cyc<90) begin
|
||||
rstn <= ~'0;
|
||||
end
|
||||
else if (cyc==99) begin
|
||||
$write("*-* All Finished *-*\n");
|
||||
$finish;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
module Test (
|
||||
input clk,
|
||||
input rstn,
|
||||
output logic [4:0] state
|
||||
);
|
||||
|
||||
logic [4:0] state_w;
|
||||
logic [4:0] state_array [3];
|
||||
assign state = state_array[0];
|
||||
|
||||
always_comb begin
|
||||
state_w[4] = state_array[2][0];
|
||||
state_w[3] = state_array[2][4];
|
||||
state_w[2] = state_array[2][3] ^ state_array[2][0];
|
||||
state_w[1] = state_array[2][2];
|
||||
state_w[0] = state_array[2][1];
|
||||
end
|
||||
|
||||
always_ff @(posedge clk or negedge rstn) begin
|
||||
if (!rstn) begin
|
||||
for (int i = 0; i < 3; i++)
|
||||
state_array[i] <= 'b1;
|
||||
end
|
||||
else begin
|
||||
for (int i = 0; i < 2; i++)
|
||||
state_array[i] <= state_array[i+1];
|
||||
state_array[2] <= state_w;
|
||||
end
|
||||
end
|
||||
|
||||
endmodule
|
||||
168
test_regress/t/t_trace_litendian_fst_sc.out
Normal file
168
test_regress/t/t_trace_litendian_fst_sc.out
Normal file
@ -0,0 +1,168 @@
|
||||
$date
|
||||
Thu Apr 1 15:29:34 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var parameter 8 ! P $end
|
||||
$var wire 1 " clk $end
|
||||
$var int 32 # cyc $end
|
||||
$var parameter 8 $ Q $end
|
||||
$var logic 1 % v_a $end
|
||||
$var logic 2 & v_b $end
|
||||
$var logic 8 ' v_c $end
|
||||
$var logic 9 ( v_d $end
|
||||
$var logic 16 ) v_e $end
|
||||
$var logic 17 * v_f $end
|
||||
$var logic 32 + v_g $end
|
||||
$var logic 33 , v_h $end
|
||||
$var logic 64 - v_i $end
|
||||
$var logic 65 . v_j $end
|
||||
$var logic 128 / v_k $end
|
||||
$var logic 129 0 v_l $end
|
||||
$var logic 256 1 v_m $end
|
||||
$var logic 257 2 v_n $end
|
||||
$var logic 512 3 v_o $end
|
||||
$var logic 3 4 v_p $end
|
||||
$var logic 15 5 v_q $end
|
||||
$var logic 31 6 v_r $end
|
||||
$var logic 63 7 v_s $end
|
||||
$var logic 127 8 v_t $end
|
||||
$var logic 255 9 v_u $end
|
||||
$var logic 511 : v_v $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 :
|
||||
b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 9
|
||||
b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 8
|
||||
b000000000000000000000000000000000000000000000000000000000000000 7
|
||||
b0000000000000000000000000000000 6
|
||||
b000000000000000 5
|
||||
b000 4
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 3
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 2
|
||||
b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 1
|
||||
b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 0
|
||||
b00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 /
|
||||
b00000000000000000000000000000000000000000000000000000000000000000 .
|
||||
b0000000000000000000000000000000000000000000000000000000000000000 -
|
||||
b000000000000000000000000000000000 ,
|
||||
b00000000000000000000000000000000 +
|
||||
b00000000000000000 *
|
||||
b0000000000000000 )
|
||||
b000000000 (
|
||||
b00000000 '
|
||||
b00 &
|
||||
0%
|
||||
b00010100 $
|
||||
b00000000000000000000000000000000 #
|
||||
0"
|
||||
b00001010 !
|
||||
$end
|
||||
#10
|
||||
1"
|
||||
b00000000000000000000000000000001 #
|
||||
1%
|
||||
b11 &
|
||||
b11111111 '
|
||||
b111111111 (
|
||||
b1111111111111111 )
|
||||
b11111111111111111 *
|
||||
b11111111111111111111111111111111 +
|
||||
b111111111111111111111111111111111 ,
|
||||
b1111111111111111111111111111111111111111111111111111111111111111 -
|
||||
b11111111111111111111111111111111111111111111111111111111111111111 .
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 /
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 0
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 1
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 2
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 3
|
||||
b111 4
|
||||
b111111111111111 5
|
||||
b1111111111111111111111111111111 6
|
||||
b111111111111111111111111111111111111111111111111111111111111111 7
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 8
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 9
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111 :
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0"
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1"
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 :
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 9
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 8
|
||||
b111111111111111111111111111111111111111111111111111111111111110 7
|
||||
b1111111111111111111111111111110 6
|
||||
b111111111111110 5
|
||||
b110 4
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 3
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 2
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 1
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 0
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111110 /
|
||||
b11111111111111111111111111111111111111111111111111111111111111110 .
|
||||
b1111111111111111111111111111111111111111111111111111111111111110 -
|
||||
b111111111111111111111111111111110 ,
|
||||
b11111111111111111111111111111110 +
|
||||
b11111111111111110 *
|
||||
b1111111111111110 )
|
||||
b111111110 (
|
||||
b11111110 '
|
||||
b10 &
|
||||
0%
|
||||
b00000000000000000000000000000010 #
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0"
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1"
|
||||
b00000000000000000000000000000011 #
|
||||
b00 &
|
||||
b11111100 '
|
||||
b111111100 (
|
||||
b1111111111111100 )
|
||||
b11111111111111100 *
|
||||
b11111111111111111111111111111100 +
|
||||
b111111111111111111111111111111100 ,
|
||||
b1111111111111111111111111111111111111111111111111111111111111100 -
|
||||
b11111111111111111111111111111111111111111111111111111111111111100 .
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 /
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 0
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 1
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 2
|
||||
b11111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 3
|
||||
b100 4
|
||||
b111111111111100 5
|
||||
b1111111111111111111111111111100 6
|
||||
b111111111111111111111111111111111111111111111111111111111111100 7
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 8
|
||||
b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 9
|
||||
b1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111100 :
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
35
test_regress/t/t_trace_litendian_fst_sc.pl
Executable file
35
test_regress/t/t_trace_litendian_fst_sc.pl
Executable file
@ -0,0 +1,35 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2020 by Geza Lore. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_litendian.v");
|
||||
|
||||
# CI environment offers 2 VCPUs, 2 thread setting causes the following warning.
|
||||
# %Warning-UNOPTTHREADS: Thread scheduler is unable to provide requested parallelism; consider asking for fewer threads.
|
||||
# Strangely, asking for more threads makes it go away.
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace-fst --trace-params -Wno-LITENDIAN',
|
||||
($Self->{vltmt} ? '--threads 6' : '')],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical("$Self->{obj_dir}/simx.fst", $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
73
test_regress/t/t_trace_packed_struct_fst_sc.out
Normal file
73
test_regress/t/t_trace_packed_struct_fst_sc.out
Normal file
@ -0,0 +1,73 @@
|
||||
$date
|
||||
Thu Apr 1 15:33:45 2021
|
||||
|
||||
$end
|
||||
$version
|
||||
fstWriter
|
||||
$end
|
||||
$timescale
|
||||
1ps
|
||||
$end
|
||||
$scope module top $end
|
||||
$scope module t $end
|
||||
$var wire 1 ! clk $end
|
||||
$var int 32 " cnt $end
|
||||
$var parameter 96 # v(0) $end
|
||||
$var parameter 96 $ v(1) $end
|
||||
$var parameter 96 % v(2) $end
|
||||
$upscope $end
|
||||
$upscope $end
|
||||
$enddefinitions $end
|
||||
#0
|
||||
$dumpvars
|
||||
b000100000000000000000000000000100001000000000000000000000000000100010000000000000000000000000000 %
|
||||
b001000000000000000000000000000100010000000000000000000000000000100100000000000000000000000000000 $
|
||||
b001100000000000000000000000000100011000000000000000000000000000100110000000000000000000000000000 #
|
||||
b00000000000000000000000000000000 "
|
||||
0!
|
||||
$end
|
||||
#10
|
||||
1!
|
||||
b00000000000000000000000000000001 "
|
||||
#11
|
||||
#12
|
||||
#13
|
||||
#14
|
||||
#15
|
||||
0!
|
||||
#16
|
||||
#17
|
||||
#18
|
||||
#19
|
||||
#20
|
||||
1!
|
||||
b00000000000000000000000000000010 "
|
||||
#21
|
||||
#22
|
||||
#23
|
||||
#24
|
||||
#25
|
||||
0!
|
||||
#26
|
||||
#27
|
||||
#28
|
||||
#29
|
||||
#30
|
||||
1!
|
||||
b00000000000000000000000000000011 "
|
||||
#31
|
||||
#32
|
||||
#33
|
||||
#34
|
||||
#35
|
||||
0!
|
||||
#36
|
||||
#37
|
||||
#38
|
||||
#39
|
||||
#40
|
||||
1!
|
||||
#41
|
||||
#42
|
||||
#43
|
||||
#44
|
||||
31
test_regress/t/t_trace_packed_struct_fst_sc.pl
Executable file
31
test_regress/t/t_trace_packed_struct_fst_sc.pl
Executable file
@ -0,0 +1,31 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_packed_struct.v");
|
||||
|
||||
compile(
|
||||
v_flags2 => ["--sc --trace-fst"]
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
|
||||
fst_identical($Self->trace_filename, $Self->{golden_filename});
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
28
test_regress/t/t_trace_primitive_fst_sc.pl
Executable file
28
test_regress/t/t_trace_primitive_fst_sc.pl
Executable file
@ -0,0 +1,28 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003-2013 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_primitive.v");
|
||||
|
||||
compile(
|
||||
v_flags2 => ["--sc --trace-fst"],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
}
|
||||
ok(1);
|
||||
1;
|
||||
29
test_regress/t/t_trace_string_fst_sc.pl
Executable file
29
test_regress/t/t_trace_string_fst_sc.pl
Executable file
@ -0,0 +1,29 @@
|
||||
#!/usr/bin/env perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you
|
||||
# can redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
|
||||
|
||||
scenarios(simulator => 1);
|
||||
|
||||
if (!$Self->have_sc) {
|
||||
skip("No SystemC installed");
|
||||
}
|
||||
else {
|
||||
top_filename("t/t_trace_string.v");
|
||||
|
||||
compile(
|
||||
verilator_flags2 => ['--sc --trace'],
|
||||
);
|
||||
|
||||
execute(
|
||||
check_finished => 1,
|
||||
);
|
||||
}
|
||||
|
||||
ok(1);
|
||||
1;
|
||||
Loading…
Reference in New Issue
Block a user