Fix seg-fault with variable of parameterized interface, bug692.

Changes

@@ -11,6 +11,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Change SYMRSVDWORD to print as warning rather than error.
 
+****  Fix seg-fault with variable of parameterized interface, bug692. [Jie Xu]
+
 ****  Fix shift corner-cases, bug765, bug766, bug768, bug772, bug776. [Clifford Wolf]
 
 ****  Fix C compiler interpreting signing, bug773. [Clifford Wolf]

src/V3LinkDot.cpp

@@ -1451,6 +1451,7 @@ private:
     virtual void visit(AstPin* nodep, AstNUser*) {
 	// Pin: Link to submodule's port
 	checkNoDot(nodep);
+	nodep->iterateChildren(*this);
 	if (!nodep->modVarp()) {
 	    if (!m_pinSymp) nodep->v3fatalSrc("Pin not under cell?\n");
 	    VSymEnt* foundp = m_pinSymp->findIdFlat(nodep->name());
@@ -1475,7 +1476,6 @@ private:
 		    refp->user5p(nodep);
 		}
 	    }
-	    nodep->iterateChildren(*this);
 	}
 	// Early return() above when deleted
     }

test_regress/t/t_interface_param1.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    v_flags2 => ["--lint-only"],
+    verilator_make_gcc => 0,
+    make_top_shell => 0,
+    make_main => 0,
+    );
+
+ok(1);
+1;

test_regress/t/t_interface_param1.v

@@ -0,0 +1,51 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Jie Xu.
+
+//bug692
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input  wire       clk;
+
+   wire [31:0] 	     result;
+   test_if  #(.id(3)) s();
+   sub_test U_SUB_TEST(s.a.b, result);  // the line causing error
+endmodule : t
+
+// ---------------------------------------------------------------------------
+
+module sub_test
+  (
+   input [31:0]  b,
+   output [31:0] c
+   );
+   assign c = b;
+endmodule
+
+// ---------------------------------------------------------------------------
+
+interface test_if
+  #(parameter id = 0)
+   ();
+
+   typedef struct     packed {
+      logic 	      a;
+      logic [31:0]    b;
+   } aType;
+
+   aType a;
+
+   typedef struct     packed {
+      logic 	      c;
+      logic [31:0]    d;
+   } bType;
+
+   bType b;
+
+   modport master (input a, output b);
+
+endinterface