diff --git a/Changes b/Changes
index c85a27952..211b5f726 100644
--- a/Changes
+++ b/Changes
@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ***   Support $past. [Dan Gisselquist]
 
+***   Support restrict, bug1350. [Clifford Wolf]
+
 ***   Fix Mac OSX 10.13.6 / LLVM 9.1  compile issues, bug1348. [Kevin Kiningham]
 
 ***   Fix MinGW compile issues, msg2636. [HyungKi Jeong]
diff --git a/src/V3Assert.cpp b/src/V3Assert.cpp
index d7b9b4ea3..5fb149f4f 100644
--- a/src/V3Assert.cpp
+++ b/src/V3Assert.cpp
@@ -145,6 +145,10 @@ private:
             // than the sim-killing else clause:
             ifp->branchPred(AstBranchPred::BP_LIKELY);
             bodysp = newIfAssertOn(ifp);
+        } else if (VN_IS(nodep, PslRestrict)) {
+            // IEEE says simulator ignores these
+            pushDeletep(nodep->unlinkFrBack()); VL_DANGLING(nodep);
+            return;
 	} else {
 	    nodep->v3fatalSrc("Unknown node type");
 	}
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index deb4f9953..2fbc7671c 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -5346,6 +5346,13 @@ public:
     AstNode* stmtsp() const { return op4p(); }  // op4 = statements
 };
 
+class AstPslAssert : public AstNodePslCoverOrAssert {
+public:
+    ASTNODE_NODE_FUNCS(PslAssert)
+    AstPslAssert(FileLine* fl, AstNode* propp, AstNode* stmtsp, const string& name="")
+        : AstNodePslCoverOrAssert(fl, propp, stmtsp, name) {}
+};
+
 class AstPslCover : public AstNodePslCoverOrAssert {
 public:
     ASTNODE_NODE_FUNCS(PslCover)
@@ -5355,11 +5362,11 @@ public:
     void coverincp(AstCoverInc* nodep) { addOp3p(nodep); }  // op3 = coverage node
 };
 
-class AstPslAssert : public AstNodePslCoverOrAssert {
+class AstPslRestrict : public AstNodePslCoverOrAssert {
 public:
-    ASTNODE_NODE_FUNCS(PslAssert)
-    AstPslAssert(FileLine* fl, AstNode* propp, AstNode* stmtsp, const string& name="")
-        : AstNodePslCoverOrAssert(fl, propp, stmtsp, name) {}
+    ASTNODE_NODE_FUNCS(PslRestrict)
+    AstPslRestrict(FileLine* fl, AstNode* propp)
+        : AstNodePslCoverOrAssert(fl, propp, NULL, "") {}
 };
 
 //======================================================================
diff --git a/src/V3LinkParse.cpp b/src/V3LinkParse.cpp
index c1597da19..0d299961e 100644
--- a/src/V3LinkParse.cpp
+++ b/src/V3LinkParse.cpp
@@ -406,6 +406,9 @@ private:
     virtual void visit(AstPslCover* nodep) {
 	visitIterateNoValueMod(nodep);
     }
+    virtual void visit(AstPslRestrict* nodep) {
+        visitIterateNoValueMod(nodep);
+    }
 
     virtual void visit(AstNode* nodep) {
 	// Default: Just iterate
diff --git a/src/verilog.l b/src/verilog.l
index c72bfc953..4b81bc301 100644
--- a/src/verilog.l
+++ b/src/verilog.l
@@ -491,6 +491,7 @@ vnum	{vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
   "pure"		{ FL; return yPURE; }
   "rand"		{ FL; return yRAND; }
   "randc"		{ FL; return yRANDC; }
+  "restrict"		{ FL; return yRESTRICT; }
   "return"		{ FL; return yRETURN; }
   "shortint"		{ FL; return ySHORTINT; }
   "static"		{ FL; return ySTATIC; }
diff --git a/src/verilog.y b/src/verilog.y
index fff35b3db..d275b874e 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -399,6 +399,7 @@ class AstSenTree;
 %token<fl>		yREALTIME	"realtime"
 %token<fl>		yREG		"reg"
 %token<fl>		yREPEAT		"repeat"
+%token<fl>		yRESTRICT	"restrict"
 %token<fl>		yRETURN		"return"
 %token<fl>		yRNMOS		"rnmos"
 %token<fl>		yRPMOS		"rpmos"
@@ -3745,6 +3746,8 @@ concurrent_assertion_statement<nodep>:	// ==IEEE: concurrent_assertion_statement
 		yASSERT yPROPERTY '(' property_spec ')' elseStmtBlock	{ $$ = new AstPslAssert($1,$4,$6); }
 	//				// IEEE: cover_property_statement
 	|	yCOVER yPROPERTY '(' property_spec ')' stmtBlock	{ $$ = new AstPslCover($1,$4,$6); }
+	//			// IEEE: restrict_property_statement
+	|	yRESTRICT yPROPERTY '(' property_spec ')' ';'		{ $$ = new AstPslRestrict($1,$4); }
 	;
 
 elseStmtBlock<nodep>:	// Part of concurrent_assertion_statement
diff --git a/test_regress/t/t_assert_property.v b/test_regress/t/t_assert_property.v
index ed6d8b799..32f225a1d 100644
--- a/test_regress/t/t_assert_property.v
+++ b/test_regress/t/t_assert_property.v
@@ -45,6 +45,8 @@ module Test
 
    assert property (@(posedge clk) cyc < 100);
 
+   restrict property (@(posedge clk) cyc==1);  // Ignored in simulators
+
 // Unclocked is not supported:
 //   assert property (cyc != 6);