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Fix UNOPTFLAT circular array bounds crossing, bug630.

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This commit is contained in:
Wilson Snyder 2013-03-08 19:25:20 -05:00
parent a767da4f3f
commit 9e29625207
4 changed files with 55 additions and 5 deletions
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2
Changes
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@ -30,6 +30,8 @@ indicates the contributor was also the author of the fix; Thanks!
**** Fix opening a VerilatedVcdC file multiple times, msg1021. [Frederic Requin]
**** Fix UNOPTFLAT circular array bounds crossing, bug630. [Jie Xu]
* Verilator 3.845 2013/02/04

9
src/V3Changed.cpp
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@ -90,13 +90,12 @@ private:
AstStructDType *structp = varp->dtypeSkipRefp()->castStructDType();
bool isArray = arrayp;
bool isStruct = structp && structp->packed();
int msb = isArray ? arrayp->msb() : 0;
int lsb = isArray ? arrayp->lsb() : 0;
if (isArray && ((msb - lsb + 1) > DETECTARRAY_MAX_INDEXES)) {
int elements = isArray ? arrayp->elementsConst() : 1;
if (isArray && (elements > DETECTARRAY_MAX_INDEXES)) {
vscp->v3warn(E_DETECTARRAY, "Unsupported: Can't detect more than "<<cvtToStr(DETECTARRAY_MAX_INDEXES)
<<" array indexes (probably with UNOPTFLAT warning suppressed): "<<varp->prettyName()<<endl
<<vscp->warnMore()
<<"... Could recompile with DETECTARRAY_MAX_INDEXES increased to at least "<<cvtToStr(msb-lsb+1));
<<"... Could recompile with DETECTARRAY_MAX_INDEXES increased to at least "<<cvtToStr(elements));
} else if (!isArray && !isStruct
&& !varp->dtypeSkipRefp()->castBasicDType()) {
if (debug()) varp->dumpTree(cout,"-DETECTARRAY-");
@ -111,7 +110,7 @@ private:
m_topModp->addStmtp(newvarp);
AstVarScope* newvscp = new AstVarScope(vscp->fileline(), m_scopetopp, newvarp);
m_scopetopp->addVarp(newvscp);
for (int index=lsb; index<=msb; ++index) {
for (int index=0; index<elements; ++index) {
AstChangeDet* changep
= new AstChangeDet (vscp->fileline(),
aselIfNeeded(isArray, index,

18
test_regress/t/t_unopt_bound.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

31
test_regress/t/t_unopt_bound.v Normal file
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@ -0,0 +1,31 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jue Xu.
// bug630
module t ( clk, out );
input clk;
output out;
reg a;
reg b;
typedef struct packed {
logic config_a;
logic config_b;
} param_t;
// verilator lint_off UNOPTFLAT
param_t conf [1:2] ;
// verilator lint_on UNOPTFLAT
always @ (posedge clk) begin
conf[2].config_b <= a;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge conf[2].config_b) begin
a = conf[2].config_a;
end
endmodule