Support arrayed parameter overrides, bug1153.

This commit is contained in:
Wilson Snyder 2017-05-02 19:16:54 -04:00
parent 8943ad5966
commit 9dc01cf540
6 changed files with 59 additions and 4 deletions

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@ -5,7 +5,9 @@ The contributors that suggested a given feature are shown in []. Thanks!
* Verilator 3.903 devel
*** Support ports of array of reals, bug1154. [J Briquet]
*** Support ports of array of reals, bug1154. [J Briquet]
*** Support arrayed parameter overrides, bug1153. [John Stevenson]
**** Fix non-arrayed cells with interface arrays, bug1153. [John Stevenson]

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@ -1491,6 +1491,14 @@ private:
did=true;
}
}
else if (m_params && valuep->castInitArray() && nodep->backp()->castPin()) {
// Allow parameters to pass arrays
// Earlier recursion of InitArray made sure each array value is constant
// This exception is fairly fragile, i.e. doesn't support arrays of arrays or other stuff
AstNode* newp = valuep->cloneTree(false);
nodep->replaceWith(newp); nodep->deleteTree(); VL_DANGLING(nodep);
did = true;
}
}
}
if (!did && m_required) {

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@ -493,6 +493,12 @@ void ParamVisitor::visitCell(AstCell* nodep) {
if (AstVar* modvarp = pinp->modVarp()) {
if (!modvarp->isGParam()) {
pinp->v3error("Attempted parameter setting of non-parameter: Param "<<pinp->prettyName()<<" of "<<nodep->prettyName());
} else if (pinp->exprp()->castInitArray()
&& modvarp->subDTypep()->castUnpackArrayDType()) {
// Array assigned to array
AstNode* exprp = pinp->exprp();
longname += "_" + paramSmallName(nodep->modp(),modvarp)+paramValueNumber(exprp);
any_overrides = true;
} else {
AstConst* exprp = pinp->exprp()->castConst();
AstConst* origp = modvarp->valuep()->castConst();
@ -651,11 +657,11 @@ void ParamVisitor::visitCell(AstCell* nodep) {
for (AstPin* pinp = nodep->paramsp(); pinp; pinp=pinp->nextp()->castPin()) {
if (pinp->exprp()) {
if (AstVar* modvarp = pinp->modVarp()) {
AstConst* constp = pinp->exprp()->castConst();
AstNode* newp = pinp->exprp(); // Const or InitArray
// Remove any existing parameter
if (modvarp->valuep()) modvarp->valuep()->unlinkFrBack()->deleteTree();
// Set this parameter to value requested by cell
modvarp->valuep(constp->cloneTree(false));
modvarp->valuep(newp->cloneTree(false));
}
else if (AstParamTypeDType* modptp = pinp->modPTypep()) {
AstNodeDType* dtypep = pinp->exprp()->castNodeDType();

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@ -873,7 +873,7 @@ vnum {vnum1}|{vnum2}|{vnum3}|{vnum4}|{vnum5}
/* Attributes */
/* Note simulators vary in support for "(* /_*something*_/ foo*)" where _ doesn't exist */
<V95,V01,V05,VA5,S05,S09,S12,SAX>{
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } // Doesn't match (*), but (* attr_spec
"(*"({ws}|{crnl})*({id}|{escid}) { yymore(); yy_push_state(ATTRMODE); } /* Doesn't match (*), but (* attr_spec */
}
/************************************************************************/

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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

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@ -0,0 +1,21 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2017 by Wilson Snyder.
module t;
localparam int c[4] = '{5, 6, 7, 8};
a #(.p(c)) i_a ();
endmodule
module a
#( parameter int p[4] = '{1, 2, 3, 4} );
initial begin
if (p[0] != 5) $stop;
if (p[1] != 6) $stop;
if (p[2] != 7) $stop;
if (p[3] != 8) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule