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Fix internal error on unique casez with --assert, bug1117.

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This commit is contained in:
Wilson Snyder 2016-12-03 14:49:51 -05:00
parent 77fe33e57f
commit 9b06310cbe
4 changed files with 67 additions and 3 deletions
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@ -7,6 +7,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
**** Fix internal error on double-for loop unrolling, bug1044. [Jan Egil Ruud]
**** Fix internal error on unique casez with --assert, bug1117. [Enzo Chi]
* Verilator 3.890 2016-11-25

23
src/V3Assert.cpp
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@ -245,9 +245,26 @@ private:
AstNode* propp = NULL;
for (AstCaseItem* itemp = nodep->itemsp(); itemp; itemp=itemp->nextp()->castCaseItem()) {
for (AstNode* icondp = itemp->condsp(); icondp!=NULL; icondp=icondp->nextp()) {
AstNode* onep = new AstEq(icondp->fileline(),
nodep->exprp()->cloneTree(false),
icondp->cloneTree(false));
AstNode* onep;
AstConst* iconstp = icondp->castConst();
if (iconstp && iconstp->num().isFourState()
&& (nodep->casex() || nodep->casez() || nodep->caseInside())) {
V3Number nummask (itemp->fileline(), iconstp->width());
nummask.opBitsNonX(iconstp->num());
V3Number numval (itemp->fileline(), iconstp->width());
numval.opBitsOne(iconstp->num());
AstNode* and1p = new AstAnd(itemp->fileline(), nodep->exprp()->cloneTree(false),
new AstConst(itemp->fileline(), nummask));
AstNode* and2p = new AstAnd(itemp->fileline(),
new AstConst(itemp->fileline(), numval),
new AstConst(itemp->fileline(), nummask));
onep = AstEq::newTyped(itemp->fileline(), and1p, and2p);
} else {
onep = AstEq::newTyped(icondp->fileline(),
nodep->exprp()->cloneTree(false),
icondp->cloneTree(false));
}
if (propp) propp = new AstConcat(icondp->fileline(), onep, propp);
else propp = onep;
}

19
test_regress/t/t_assert_casez.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
verilator_flags2 => ['--assert'],
);
execute (
check_finished=>1,
);
ok(1);
1;

26
test_regress/t/t_assert_casez.v Normal file
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@ -0,0 +1,26 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2016 by Wilson Snyder
module t;
reg [1:0] value;
initial begin
value = 2'b00;
unique casez (value)
2'b00 : ;
2'b01 : ;
2'b1? : ;
endcase
value = 2'b11;
unique casez (value)
2'b00 : ;
2'b01 : ;
2'b1? : ;
endcase
$write("*-* All Finished *-*\n");
$finish;
end
endmodule