forked from github/verilator
Internals: More UASSERT_OBJ conversions. No functional change intended.
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4ce77d3e68
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9af84c71f5
@ -215,8 +215,8 @@ string AstVar::verilogKwd() const {
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}
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string AstVar::vlArgType(bool named, bool forReturn, bool forFunc) const {
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if (forReturn) named = false;
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if (forReturn) v3fatalSrc("verilator internal data is never passed as return, but as first argument");
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UASSERT_OBJ(!forReturn, this,
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"Internal data is never passed as return, but as first argument");
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string otype;
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AstBasicDType* bdtypep = basicp();
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bool strtype = bdtypep && bdtypep->keyword()==AstBasicDTypeKwd::STRING;
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@ -951,8 +951,8 @@ class AstSelBit : public AstNodePreSel {
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public:
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AstSelBit(FileLine* fl, AstNode* fromp, AstNode* bitp)
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:AstNodePreSel(fl, fromp, bitp, NULL) {
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if (v3Global.assertDTypesResolved()) { v3fatalSrc("not coded to create after dtypes resolved"); }
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}
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UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
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"not coded to create after dtypes resolved"); }
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ASTNODE_NODE_FUNCS(SelBit)
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AstNode* bitp() const { return rhsp(); }
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};
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@ -3860,8 +3860,8 @@ class AstSigned : public AstNodeUniop {
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// $signed(lhs)
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public:
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AstSigned(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
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if (v3Global.assertDTypesResolved()) { v3fatalSrc("not coded to create after dtypes resolved"); }
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}
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UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
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"not coded to create after dtypes resolved"); }
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ASTNODE_NODE_FUNCS(Signed)
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virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); out.isSigned(false); }
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virtual string emitVerilog() { return "%f$signed(%l)"; }
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@ -3875,8 +3875,8 @@ class AstUnsigned : public AstNodeUniop {
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// $unsigned(lhs)
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public:
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AstUnsigned(FileLine* fl, AstNode* lhsp) : AstNodeUniop(fl, lhsp) {
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if (v3Global.assertDTypesResolved()) { v3fatalSrc("not coded to create after dtypes resolved"); }
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}
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UASSERT_OBJ(!v3Global.assertDTypesResolved(), this,
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"not coded to create after dtypes resolved"); }
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ASTNODE_NODE_FUNCS(Unsigned)
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virtual void numberOperate(V3Number& out, const V3Number& lhs) { out.opAssign(lhs); out.isSigned(false); }
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virtual string emitVerilog() { return "%f$unsigned(%l)"; }
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