forked from github/verilator
Tests: Allow driver to find 't' signals when not first in file.
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@ -1297,14 +1297,23 @@ sub _read_inputs_v {
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my $filename = $self->top_filename;
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my $filename = $self->top_filename;
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$filename = "$self->{t_dir}/$filename" if !-r $filename;
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$filename = "$self->{t_dir}/$filename" if !-r $filename;
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my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,";
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my $fh = IO::File->new("<$filename") or die "%Error: $! $filename,";
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my $get_sigs=1;
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my %inputs;
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while (defined(my $line = $fh->getline)) {
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while (defined(my $line = $fh->getline)) {
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if ($line =~ /^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;/) {
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if ($get_sigs) {
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$self->{inputs}{$1} = $1;
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if ($line =~ /^\s*input\s*(\S+)\s*(\/[^\/]+\/|)\s*;/) {
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$inputs{$1} = $1;
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}
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if ($line =~ /^\s*(function|task|endmodule)/) {
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$get_sigs = 0;
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}
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}
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}
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if ($line =~ /^\s*(function|task|endmodule)/) {
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if ($line =~ /^\s*module\s+t\b/) { # Ignore any earlier inputs; Module 't' has precedence
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last;
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%inputs = ();
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$get_sigs = 1;
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}
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}
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}
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}
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$self->{inputs}{$_} = $inputs{$_} foreach keys %inputs;
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$fh->close();
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$fh->close();
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}
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}
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