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Support parsing min:typ:max parameters

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This commit is contained in:
Wilson Snyder 2023-03-01 23:11:48 -05:00
parent a85e6a9d8c
commit 976af0068b
3 changed files with 40 additions and 2 deletions
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4
src/verilog.y
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@ -2940,7 +2940,7 @@ delay_control<delayp>: //== IEEE: delay_control
| '#' '(' minTypMax ',' minTypMax ')'
{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); }
| '#' '(' minTypMax ',' minTypMax ',' minTypMax ')'
{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($3); DEL($5); DEL($7); }
{ $$ = new AstDelay{$<fl>1, $3, false}; RISEFALLDLYUNSUP($5); DEL($3); DEL($7); }
;
delay_value<nodeExprp>: // ==IEEE:delay_value
@ -4785,7 +4785,7 @@ expr<nodeExprp>: // IEEE: part of expression/constant_expression/
// // IEEE: '(' mintypmax_expression ')'
| ~noPar__IGNORE~'(' expr ')' { $$ = $2; }
| ~noPar__IGNORE~'(' expr ':' expr ':' expr ')'
{ $$ = $2; BBUNSUP($1, "Unsupported: min typ max expressions"); }
{ $$ = $4; MINTYPMAXDLYUNSUP($4); DEL($2); DEL($6); }
// // PSL rule
| '_' '(' expr ')' { $$ = $3; } // Arbitrary Verilog inside PSL
//

21
test_regress/t/t_param_mintypmax.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

17
test_regress/t/t_param_mintypmax.v Normal file
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@ -0,0 +1,17 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/);
parameter MTM = (1:2:3);
initial begin
if (MTM != 2) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule