On WIDTH warnings, show variable name causing error. - Missing files

test_regress/t/t_lint_width_bad.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 v_flags2 => ["--lint-only"],
+	 fails=>1,
+	 expect=>
+q{.*%Warning-WIDTH: t/t_lint_width_bad.v:\d+: Operator ASSIGNW expects 5 bits on the Assign RHS, but Assign RHS's VARREF 'in' generates 4 bits.
+%Warning-WIDTH: Use .*
+%Error: Exiting due to.*},
+	 ) if $Self->{v3};
+
+ok(1);
+1;

test_regress/t/t_lint_width_bad.v

@@ -0,0 +1,19 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t ();
+
+   // This shows the uglyness in width warnings across param modules
+   // TODO: Would be nice to also show relevant parameter settings
+   p #(.WIDTH(4)) p4 (.in(4'd0));
+   p #(.WIDTH(5)) p5 (.in(5'd0));
+
+endmodule
+
+module p
+  #(parameter WIDTH=64)
+   (input [WIDTH-1:0] in);
+   wire [4:0] out = in;
+endmodule