From 9699192de8f3c4a77d686c53c85963e8eb6c72b7 Mon Sep 17 00:00:00 2001
From: Geza Lore <gezalore@gmail.com>
Date: Tue, 18 May 2021 19:28:48 +0100
Subject: [PATCH] Don't merge bit select assignments in C code (#2971)

---
 Changes                                        |  1 +
 src/V3Const.cpp                                |  2 +-
 test_regress/t/t_no_sel_assign_merge_in_cpp.pl | 16 ++++++++++++++++
 test_regress/t/t_no_sel_assign_merge_in_cpp.v  | 14 ++++++++++++++
 4 files changed, 32 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_no_sel_assign_merge_in_cpp.pl
 create mode 100644 test_regress/t/t_no_sel_assign_merge_in_cpp.v

diff --git a/Changes b/Changes
index c5888960a..4951e63e9 100644
--- a/Changes
+++ b/Changes
@@ -14,6 +14,7 @@ Verilator 4.203 devel
 **Minor:**
 
 * Fix initialization of assoc in assoc array (#2914). [myftptoyman]
+* Fix merging of assignments in C++ code (#2970). [Ruper Swarbrick]
 
 
 Verilator 4.202 2021-04-24
diff --git a/src/V3Const.cpp b/src/V3Const.cpp
index f802d5524..7c78cb314 100644
--- a/src/V3Const.cpp
+++ b/src/V3Const.cpp
@@ -1719,7 +1719,7 @@ private:
             VL_DO_DANGLING(streamp->deleteTree(), streamp);
             // Further reduce, any of the nodes may have more reductions.
             return true;
-        } else if (replaceAssignMultiSel(nodep)) {
+        } else if (m_doV && replaceAssignMultiSel(nodep)) {
             return true;
         }
         return false;
diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.pl b/test_regress/t/t_no_sel_assign_merge_in_cpp.pl
new file mode 100755
index 000000000..72441b2f8
--- /dev/null
+++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.pl
@@ -0,0 +1,16 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2021 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(vlt => 1);
+
+lint();
+
+ok(1);
+1;
diff --git a/test_regress/t/t_no_sel_assign_merge_in_cpp.v b/test_regress/t/t_no_sel_assign_merge_in_cpp.v
new file mode 100644
index 000000000..6c7f1a62b
--- /dev/null
+++ b/test_regress/t/t_no_sel_assign_merge_in_cpp.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2021 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t_no_sel_assign_merge_in_cpp (
+  input  wire [(8*39)-1:0] d_i,
+  output wire [(8*32)-1:0] d_o
+);
+  for (genvar i = 0; i < 8; i = i + 1) begin
+    assign d_o[i*32 +: 32] = d_i[i*39 +: 32];
+  end
+endmodule