diff --git a/Changes b/Changes
index 1541a09df..624ac0552 100644
--- a/Changes
+++ b/Changes
@@ -35,6 +35,7 @@ Verilator 5.009 devel
 * Fix clocking block scope internal error (#4032). [Srinivasan Venkataramanan]
 * Fix false LATCH warning on --assert 'unique else if' (#4033) ($4054). [Jesse Taube]
 * Fix characters from DEFENV literals for conda (#4035) (#4044). [Tim Snyder]
+* Fix interface generate begin (#4065). [Srinivasan Venkataramanan]
 * Fix false ENUMVALUE on expressions and arrays.
 
 
diff --git a/src/verilog.y b/src/verilog.y
index e2e0cd2e2..eb06172e6 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -1636,7 +1636,7 @@ interface_item<nodep>:          // IEEE: interface_item + non_port_interface_ite
                 port_declaration ';'                    { $$ = $1; }
         //                      // IEEE: non_port_interface_item
         //                      // IEEE: generate_region
-        |       interface_generate_region               { $$ = $1; }
+        |       i_generate_region                       { $$ = $1; }
         |       interface_or_generate_item              { $$ = $1; }
         |       program_declaration
                         { $$ = nullptr; BBUNSUP(CRELINE(), "Unsupported: program decls within interface decls"); }
@@ -1649,11 +1649,6 @@ interface_item<nodep>:          // IEEE: interface_item + non_port_interface_ite
         |       module_common_item                      { $$ = $1; }
         ;
 
-interface_generate_region<nodep>:               // ==IEEE: generate_region
-                yGENERATE interface_itemList yENDGENERATE       { $$ = $2; }
-        |       yGENERATE yENDGENERATE                  { $$ = nullptr; }
-        ;
-
 interface_or_generate_item<nodep>:  // ==IEEE: interface_or_generate_item
         //                          // module_common_item in interface_item, as otherwise duplicated
         //                          // with module_or_generate_item's module_common_item
@@ -2733,6 +2728,10 @@ c_generate_region<nodep>:  // IEEE: generate_region (for checkers)
                 BISONPRE_COPY(generate_region,{s/~c~/c_/g})     // {copied}
         ;
 
+i_generate_region<nodep>:  // IEEE: generate_region (for interface)
+                BISONPRE_COPY(generate_region,{s/~c~/i_/g})     // {copied}
+        ;
+
 generate_block_or_null<nodep>:  // IEEE: generate_block_or_null (called from gencase/genif/genfor)
         //      ';'             // is included in
         //                      // IEEE: generate_block
@@ -2765,6 +2764,10 @@ c_genItemBegin<nodep>:  // IEEE: part of generate_block (for checkers)
                 BISONPRE_COPY(genItemBegin,{s/~c~/c_/g})                // {copied}
         ;
 
+i_genItemBegin<nodep>:  // IEEE: part of generate_block (for interfaces)
+                BISONPRE_COPY(genItemBegin,{s/~c~/i_/g})                // {copied}
+        ;
+
 genItemOrBegin<nodep>:          // Not in IEEE, but our begin isn't under generate_item
                 ~c~generate_item                        { $$ = $1; }
         |       ~c~genItemBegin                         { $$ = $1; }
@@ -2774,6 +2777,11 @@ c_genItemOrBegin<nodep>:  // (for checkers)
                 BISONPRE_COPY(genItemOrBegin,{s/~c~/c_/g})      // {copied}
         ;
 
+i_genItemOrBegin<nodep>:  // (for interfaces)
+                interface_item                          { $$ = $1; }
+        |       i_genItemBegin                          { $$ = $1; }
+        ;
+
 genItemList<nodep>:
                 ~c~genItemOrBegin                       { $$ = $1; }
         |       ~c~genItemList ~c~genItemOrBegin        { $$ = addNextNull($1, $2); }
@@ -2783,6 +2791,10 @@ c_genItemList<nodep>:  // (for checkers)
                 BISONPRE_COPY(genItemList,{s/~c~/c_/g})         // {copied}
         ;
 
+i_genItemList<nodep>:  // (for interfaces)
+                BISONPRE_COPY(genItemList,{s/~c~/i_/g})         // {copied}
+        ;
+
 generate_item<nodep>:           // IEEE: module_or_interface_or_generate_item
         //                      // Only legal when in a generate under a module (or interface under a module)
                 module_or_generate_item                 { $$ = $1; }
diff --git a/test_regress/t/t_interface_gen13.pl b/test_regress/t/t_interface_gen13.pl
new file mode 100755
index 000000000..f60fd309f
--- /dev/null
+++ b/test_regress/t/t_interface_gen13.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_interface_gen13.v b/test_regress/t/t_interface_gen13.v
new file mode 100644
index 000000000..0435dda0e
--- /dev/null
+++ b/test_regress/t/t_interface_gen13.v
@@ -0,0 +1,59 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty.
+// SPDX-License-Identifier: CC0-1.0
+
+// bug998
+
+interface intf
+  #(parameter PARAM = 0)
+   ();
+
+   int p1;
+   generate
+      initial p1 = 1;
+   endgenerate
+
+   int p2;
+   generate begin
+      initial p2 = 1;
+   end
+   endgenerate
+
+   int p3;
+   int p3_no;
+   if (PARAM == 1) initial p3 = 1; else initial p3_no = 1;
+
+   int p4;
+   int p4_no;
+   case (PARAM)
+     1: initial p4 = 1;
+     default: initial p4_no = 1;
+   endcase
+
+   int p5;
+   for (genvar g=0; g<=PARAM; ++g) initial p5 = 1;
+
+endinterface
+
+module t(/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   intf #(.PARAM(1)) my_intf ();
+
+   always @ (posedge clk) begin
+      if (my_intf.p1 != 1) $stop;
+      if (my_intf.p2 != 1) $stop;
+      if (my_intf.p3 != 1) $stop;
+      if (my_intf.p3_no != 0) $stop;
+      if (my_intf.p4 != 1) $stop;
+      if (my_intf.p4_no != 0) $stop;
+      if (my_intf.p5 != 1) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule