From 93782597791ba1de8dc517d6f63c49a78ebf668d Mon Sep 17 00:00:00 2001
From: Kamil Rakoczy <krakoczy@antmicro.com>
Date: Fri, 6 May 2022 10:24:03 +0200
Subject: [PATCH] Fix UNOPTFLAT warning from initial static var (#3406)

Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
---
 src/V3Order.cpp                        |  7 ++++--
 test_regress/t/t_initialstatic_circ.pl | 21 +++++++++++++++++
 test_regress/t/t_initialstatic_circ.v  | 31 ++++++++++++++++++++++++++
 3 files changed, 57 insertions(+), 2 deletions(-)
 create mode 100755 test_regress/t/t_initialstatic_circ.pl
 create mode 100644 test_regress/t/t_initialstatic_circ.v

diff --git a/src/V3Order.cpp b/src/V3Order.cpp
index 9007ce8f2..4f2890be6 100644
--- a/src/V3Order.cpp
+++ b/src/V3Order.cpp
@@ -1133,6 +1133,10 @@ class OrderProcess final : VNDeleter {
         return name;
     }
 
+    bool nodeIsInitial(const OrderLogicVertex* LVtxp) {
+        return LVtxp && (VN_IS(LVtxp->nodep(), Initial) || VN_IS(LVtxp->nodep(), InitialStatic));
+    }
+
     void nodeMarkCircular(OrderVarVertex* vertexp, OrderEdge* edgep) {
         // To be marked circular requires being a clock assigned in a delayed assignment, or
         // having a cutable in or out edge, none of which is true for the DPI export trigger.
@@ -1146,8 +1150,7 @@ class OrderProcess final : VNDeleter {
             toLVtxp = dynamic_cast<OrderLogicVertex*>(edgep->top());
         }
         //
-        if ((fromLVtxp && VN_IS(fromLVtxp->nodep(), Initial))
-            || (toLVtxp && VN_IS(toLVtxp->nodep(), Initial))) {
+        if (nodeIsInitial(fromLVtxp) || nodeIsInitial(toLVtxp)) {
             // IEEE does not specify ordering between initial blocks, so we
             // can do whatever we want. We especially do not want to
             // evaluate multiple times, so do not mark the edge circular
diff --git a/test_regress/t/t_initialstatic_circ.pl b/test_regress/t/t_initialstatic_circ.pl
new file mode 100755
index 000000000..f5e338520
--- /dev/null
+++ b/test_regress/t/t_initialstatic_circ.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2022 by Antmicro Ltd. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    );
+
+execute(
+    check_finished => 1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_initialstatic_circ.v b/test_regress/t/t_initialstatic_circ.v
new file mode 100644
index 000000000..31325cad5
--- /dev/null
+++ b/test_regress/t/t_initialstatic_circ.v
@@ -0,0 +1,31 @@
+// DESCRIPTION::Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2022 by Antmicro Ltd.
+// SPDX-License-Identifier: CC0-1.0
+
+package pkg;
+  int unsigned id = 0;
+
+  function int unsigned func();
+    int unsigned local_id;
+    local_id  = id + 1;
+    id = local_id;
+    return local_id;
+  endfunction : func
+endpackage
+
+module t(/*AUTOARG*/
+  // Inputs
+  clk
+  );
+  input clk;
+  import pkg::*;
+  int unsigned func_id = func();
+
+  always @ (posedge clk) begin
+    $display(id);
+    $write("*-* All Finished *-*\n");
+    $finish;
+  end
+endmodule