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Tests: Improve short circuit test

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This commit is contained in:
Wilson Snyder 2023-04-01 23:10:05 -04:00
parent fc5a5ea53d
commit 921fd919b5
3 changed files with 44 additions and 24 deletions

38
test_regress/t/t_dpi_shortcircuit.out
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@ -1,18 +1,22 @@
%Error: Line 60: Bad result, got=1 expect=0
%Error: Line 64: Bad result, got=1 expect=0
%Error: Line 75: Bad result, got=0 expect=1
%Error: Line 98: Bad result, got=1 expect=0
%Error: Line 102: Bad result, got=1 expect=0
%Error: Line 112: Bad result, got=0 expect=1
%Error: Line 132: Bad result, got=1 expect=0
%Error: Line 136: Bad result, got=1 expect=0
%Error: Line 150: Bad result, got=1 expect=0
%Error: Line 154: Bad result, got=1 expect=0
%Error: Line 163: Bad result, got=0 expect=1
%Error: Line 203: Bad result, got=64 expect=32
%Error: Line 204: Bad result, got=64 expect=16
%Error: Line 205: Bad result, got=64 expect=16
%Error: Line 206: Bad result, got=64 expect=36
%Error: Line 207: Bad result, got=64 expect=46
%Error: t/t_dpi_shortcircuit.v:209: Verilog $stop
%Error: Line 62: Bad result, got=1 expect=0
%Error: Line 66: Bad result, got=1 expect=0
%Error: Line 69: Bad result, got=0 expect=1
%Error: Line 81: Bad result, got=0 expect=1
%Error: Line 91: Bad result, got=0 expect=1
%Error: Line 108: Bad result, got=1 expect=0
%Error: Line 112: Bad result, got=1 expect=0
%Error: Line 114: Bad result, got=0 expect=1
%Error: Line 126: Bad result, got=0 expect=1
%Error: Line 136: Bad result, got=0 expect=1
%Error: Line 148: Bad result, got=1 expect=0
%Error: Line 152: Bad result, got=1 expect=0
%Error: Line 166: Bad result, got=1 expect=0
%Error: Line 170: Bad result, got=1 expect=0
%Error: Line 179: Bad result, got=0 expect=1
%Error: Line 219: Bad result, got=64 expect=32
%Error: Line 220: Bad result, got=64 expect=16
%Error: Line 221: Bad result, got=64 expect=16
%Error: Line 222: Bad result, got=64 expect=36
%Error: Line 223: Bad result, got=64 expect=46
%Error: t/t_dpi_shortcircuit.v:225: Verilog $stop
Aborting...

28
test_regress/t/t_dpi_shortcircuit.v
View File

@ -54,6 +54,8 @@ module t (/*AUTOARG*/);
check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0);
check1(`__LINE__, (dpii_inc0(10) && 1'b0), 1'b0);
check1(`__LINE__, (dpii_inc0(11) && 1'b1), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
@ -64,6 +66,8 @@ module t (/*AUTOARG*/);
check (`__LINE__, dpii_count(7), 0);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
check (`__LINE__, dpii_count(10), 1);
check (`__LINE__, dpii_count(11), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0);
@ -72,6 +76,8 @@ module t (/*AUTOARG*/);
check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0);
check1(`__LINE__, (dpii_inc0(10) & 1'b0), 1'b0);
check1(`__LINE__, (dpii_inc0(11) & 1'b1), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
@ -82,6 +88,8 @@ module t (/*AUTOARG*/);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
check (`__LINE__, dpii_count(10), 1);
check (`__LINE__, dpii_count(11), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0);
@ -90,6 +98,8 @@ module t (/*AUTOARG*/);
check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0);
check1(`__LINE__, (dpii_inc0(10) || 1'b0), 1'b0);
check1(`__LINE__, (dpii_inc0(11) || 1'b1), 1'b1);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 0);
check (`__LINE__, dpii_count(2), 1);
@ -100,6 +110,8 @@ module t (/*AUTOARG*/);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 0);
check (`__LINE__, dpii_count(10), 1);
check (`__LINE__, dpii_count(11), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0);
@ -108,6 +120,8 @@ module t (/*AUTOARG*/);
check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0);
check1(`__LINE__, (dpii_inc0(10) | 1'b0), 1'b0);
check1(`__LINE__, (dpii_inc0(11) | 1'b1), 1'b1);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
@ -118,6 +132,8 @@ module t (/*AUTOARG*/);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
check (`__LINE__, dpii_count(10), 1);
check (`__LINE__, dpii_count(11), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1);
@ -192,12 +208,12 @@ module t (/*AUTOARG*/);
// Something a lot more complicated
dpii_clear();
for (i=0; i<64; i++) begin
b = ( ((dpii_incx(0,i[0])
&& (dpii_incx(1,i[1])
|| dpii_incx(2,i[2])
| dpii_incx(3,i[3]))) // | not ||
|| dpii_incx(4,i[4]))
-> dpii_incx(5,i[5]));
b = ( ((dpii_incx(0,i[0])
&& (dpii_incx(1,i[1])
|| dpii_incx(2,i[2])
| dpii_incx(3,i[3]))) // | not ||
|| dpii_incx(4,i[4]))
-> dpii_incx(5,i[5]));
end
check (`__LINE__, dpii_count(0), 64);
check (`__LINE__, dpii_count(1), 32);

2
test_regress/t/t_dpi_shortcircuit_c.cpp
View File

@ -54,7 +54,7 @@ void dpii_clear() {
}
int dpii_count(int idx) { return (idx >= 0 && idx < COUNTERS) ? global_count[idx] : -1; }
unsigned char dpii_incx(int idx, unsigned char value) {
if (idx >= 0 && idx < COUNTERS) global_count[idx]++;
if (idx >= 0 && idx < COUNTERS) ++global_count[idx];
return value;
}
unsigned char dpii_inc0(int idx) { return dpii_incx(idx, 0); }