From 910803e6dbd7b77bb7dcba77dc42d4507efe1b71 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 27 Apr 2020 18:38:30 -0400
Subject: [PATCH] Fix error on unpacked connecting to packed, #2288.

---
 Changes                                 |  2 ++
 src/V3Width.cpp                         |  6 +++---
 test_regress/t/t_inst_misarray2_bad.out |  5 +++++
 test_regress/t/t_inst_misarray2_bad.pl  | 20 ++++++++++++++++++++
 test_regress/t/t_inst_misarray2_bad.v   | 17 +++++++++++++++++
 test_regress/t/t_inst_misarray_bad.out  |  6 +++---
 6 files changed, 50 insertions(+), 6 deletions(-)
 create mode 100644 test_regress/t/t_inst_misarray2_bad.out
 create mode 100755 test_regress/t/t_inst_misarray2_bad.pl
 create mode 100644 test_regress/t/t_inst_misarray2_bad.v

diff --git a/Changes b/Changes
index 03d6ec43f..d77e97f71 100644
--- a/Changes
+++ b/Changes
@@ -36,6 +36,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix arrayed instances connecting to slices, #2263. [Don/engr248]
 
+****  Fix error on unpacked connecting to packed, #2288. [Joseph Shaker]
+
 
 * Verilator 4.032 2020-04-04
 
diff --git a/src/V3Width.cpp b/src/V3Width.cpp
index 940adb4fb..a80ab2073 100644
--- a/src/V3Width.cpp
+++ b/src/V3Width.cpp
@@ -3519,13 +3519,13 @@ private:
                                    << exprSize << ".");
                     UINFO(1, "    Related lo: " << modDTypep->skipRefp() << endl);
                     UINFO(1, "    Related hi: " << exprDTypep->skipRefp() << endl);
-                } else if ((exprArrayp && !modArrayp && pinwidth != conwidth)
-                           || (!exprArrayp && modArrayp && pinwidth != conwidth)) {
+                } else if ((exprArrayp && !modArrayp) || (!exprArrayp && modArrayp)) {
                     nodep->v3error("Illegal " << nodep->prettyOperatorName() << ","
                                               << " mismatch between port which is"
                                               << (modArrayp ? "" : " not") << " an array,"
                                               << " and expression which is"
-                                              << (exprArrayp ? "" : " not") << " an array.");
+                                              << (exprArrayp ? "" : " not")
+                                              << " an array. (IEEE 1800-2017 7.6)");
                     UINFO(1, "    Related lo: " << modDTypep->skipRefp() << endl);
                     UINFO(1, "    Related hi: " << exprDTypep->skipRefp() << endl);
                 }
diff --git a/test_regress/t/t_inst_misarray2_bad.out b/test_regress/t/t_inst_misarray2_bad.out
new file mode 100644
index 000000000..889bfcc7c
--- /dev/null
+++ b/test_regress/t/t_inst_misarray2_bad.out
@@ -0,0 +1,5 @@
+%Error: t/t_inst_misarray2_bad.v:10:17: Illegal input port connection 'i_data', mismatch between port which is not an array, and expression which is an array. (IEEE 1800-2017 7.6)
+                                      : ... In instance t
+   10 |                .i_data(fft_oQ[6:0])
+      |                 ^~~~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_inst_misarray2_bad.pl b/test_regress/t/t_inst_misarray2_bad.pl
new file mode 100755
index 000000000..32c62a917
--- /dev/null
+++ b/test_regress/t/t_inst_misarray2_bad.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inst_misarray2_bad.v b/test_regress/t/t_inst_misarray2_bad.v
new file mode 100644
index 000000000..dc55dcad4
--- /dev/null
+++ b/test_regress/t/t_inst_misarray2_bad.v
@@ -0,0 +1,17 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t (/*AUTOARG*/);
+   wire signed [16:0] fft_oQ [6:0];
+   round round(
+               .i_data(fft_oQ[6:0])
+               );
+endmodule
+module round(
+             input wire signed [16:0] i_data  // Misdeclared, not a vector
+             );
+   wire signed [15:0] w_convergent = {10'b0, {6{~i_data[7]}}};
+endmodule
diff --git a/test_regress/t/t_inst_misarray_bad.out b/test_regress/t/t_inst_misarray_bad.out
index 0e0a9a157..56dd2368a 100644
--- a/test_regress/t/t_inst_misarray_bad.out
+++ b/test_regress/t/t_inst_misarray_bad.out
@@ -1,5 +1,5 @@
-%Error: t/t_inst_misarray_bad.v:17:27: VARREF 't.foo' is not an unpacked array, but is in an unpacked array context
-                                     : ... In instance t.foo
+%Error: t/t_inst_misarray_bad.v:17:23: Illegal input port connection 'foo', mismatch between port which is an array, and expression which is not an array. (IEEE 1800-2017 7.6)
+                                     : ... In instance t
    17 |                      .foo(foo));   
-      |                           ^~~
+      |                       ^~~
 %Error: Exiting due to