Fix non-ANSI modport instantiations, bug868.

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix VM_PARALLEL_BUILDS broke in 3.868, bug870. [Hiroki Honda]
 
+****  Fix non-ANSI modport instantiations, bug868. [Kevin Thompson]
+
 
 * Verilator 3.868 2014-12-20
 

src/verilog.y

@@ -1237,6 +1237,9 @@ port_declaration<nodep>:	// ==IEEE: port_declaration
 			list_of_variable_decl_assignments			{ $$ = $5; }
 	|	port_directionReset port_declNetE /*implicit*/       { VARDTYPE(NULL);/*default_nettype*/}
 			list_of_variable_decl_assignments			{ $$ = $4; }
+	//			// IEEE: interface_declaration
+	//			// Looks just like variable declaration unless has a period
+	//			// See etcInst
 	;
 
 tf_port_declaration<nodep>:	// ==IEEE: tf_port_declaration
@@ -2011,9 +2014,24 @@ etcInst<nodep>:			// IEEE: module_instantiation + gate_instantiation + udp_insta
 instDecl<nodep>:
 		id parameter_value_assignmentE {INSTPREP(*$1,$2);} instnameList ';'
 			{ $$ = $4; GRAMMARP->m_impliedDecl=false;}
+	//			// IEEE: interface_identifier' .' modport_identifier list_of_interface_identifiers
+	|	id/*interface*/ '.' id/*modport*/
+			{ VARRESET_NONLIST(AstVarType::IFACEREF);
+			  VARDTYPE(new AstIfaceRefDType($<fl>1,"",*$1,*$3)); }
+		mpInstnameList ';'
+			{ $$ = VARDONEP($5,NULL,NULL); }
 	//UNSUP: strengthSpecE for udp_instantiations
 	;
 
+mpInstnameList<nodep>:		// Similar to instnameList, but for modport instantiations which have no parenthesis
+		mpInstnameParen				{ $$ = $1; }
+	|	mpInstnameList ',' mpInstnameParen	{ $$ = $1->addNext($3); }
+	;
+
+mpInstnameParen<nodep>:		// Similar to instnameParen, but for modport instantiations which have no parenthesis
+		id instRangeE sigAttrListE		{ $$ = VARDONEA($<fl>1,*$1,$2,$3); }
+	;
+
 instnameList<nodep>:
 		instnameParen				{ $$ = $1; }
 	|	instnameList ',' instnameParen		{ $$ = $1->addNext($3); }

test_regress/t/t_interface1_modport.v

@@ -37,10 +37,18 @@ module t (/*AUTOARG*/
 endmodule
 
 module sub
+`ifdef NANSI  // bug868
+  (
+   isub, i_value
+   );
+   ifc.out_modport isub;   // Note parenthesis are not legal here
+   input integer i_value;
+`else
   (
    ifc.out_modport isub,
    input integer i_value
    );
+`endif
 
    always @* begin
       isub.value = i_value;

test_regress/t/t_interface1_modport_nansi.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2009 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_interface1_modport.v");
+
+compile (
+    v_flags2 => ['+define+NANSI'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;