forked from github/verilator
Fix unnamedblk error on foreach (#3321).
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3
Changes
@ -21,8 +21,9 @@ Verilator 4.219 devel
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* Fix $readmem file not found to be warning not error (#3310). [Alexander Grobman]
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* Fix class stringification on wide arrays (#3312). [Iru Cai]
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* Fix public function arguments that are arrayed (#3316). [pawel256]
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* Fix compile error with --trace-fst --sc (#3332). [leavinel]
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* Fix unnamedblk error on foreach (#3321). [Aliaksei Chapyzhenka]
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* Fix crash in recursive module inlining (#3324). [Larry Doolittle]
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* Fix compile error with --trace-fst --sc (#3332). [leavinel]
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Verilator 4.218 2022-01-17
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@ -942,7 +942,7 @@ class LinkDotFindVisitor final : public VNVisitor {
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// places such as tasks, where "task ...; begin ... end"
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// are common.
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for (AstNode* stmtp = nodep->stmtsp(); stmtp; stmtp = stmtp->nextp()) {
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if (VN_IS(stmtp, Var)) {
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if (VN_IS(stmtp, Var) || VN_IS(stmtp, Foreach)) {
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++m_modBlockNum;
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nodep->name("unnamedblk" + cvtToStr(m_modBlockNum));
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break;
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21
test_regress/t/t_foreach_iface.pl
Executable file
21
test_regress/t/t_foreach_iface.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2022 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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);
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execute(
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check_finished => 1,
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);
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ok(1);
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1;
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28
test_regress/t/t_foreach_iface.v
Normal file
28
test_regress/t/t_foreach_iface.v
Normal file
@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2022 by Pawel Jewstafjew (Pawel.Jewstafjew@gmail.com).
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// SPDX-License-Identifier: CC0-1.0
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interface Iface (input bit [31:0] regs [1]);
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initial begin
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string instance_path = $sformatf("%m");
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$display("Iface path %s\n", instance_path);
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$write("*-* All Finished *-*\n");
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$finish;
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end
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bit [0:0] ppp;
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always_comb begin
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// Ok:
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//for (int index = 1 ; index < 2 ; ++index) begin
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foreach (regs[index]) begin
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ppp[index] = 1;
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end
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end
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endinterface
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module top (input bit [31:0] regs [1]);
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Iface t1(.regs(regs));
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endmodule
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