From 8c9ca7a1b3e990b6ceae0b0d85fce97adead4f09 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Wed, 13 Sep 2017 19:09:49 -0400 Subject: [PATCH] Fix LITENDIAN warning on arrayed cells, bug1202. --- Changes | 2 ++ bin/verilator | 5 +++ src/V3Inst.cpp | 4 +++ src/V3Width.cpp | 3 +- test_regress/t/t_interface_array_nocolon.v | 7 +++- .../t/t_interface_array_nocolon_bad.pl | 23 +++++++++++++ .../t/t_interface_array_nocolon_bad.v | 32 +++++++++++++++++++ 7 files changed, 74 insertions(+), 2 deletions(-) create mode 100755 test_regress/t/t_interface_array_nocolon_bad.pl create mode 100644 test_regress/t/t_interface_array_nocolon_bad.v diff --git a/Changes b/Changes index e8e3a36d2..4624fc8c8 100644 --- a/Changes +++ b/Changes @@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks! *** Fix ordering of arrayed cell wide connections, bug1202 partial. [Mike Popoloski] +**** Fix LITENDIAN warning on arrayed cells, bug1202. [Mike Popoloski] + **** Fix enum ranges without colons, bug1204. [Mike Popoloski] diff --git a/bin/verilator b/bin/verilator index 8f442444d..365a4949c 100755 --- a/bin/verilator +++ b/bin/verilator @@ -3205,6 +3205,11 @@ Warns that a packed vector is declared with little endian bit numbering and little numbering is now thus often due to simple oversight instead of intent. +Also warns that a cell is declared with little endian range (i.e. [0:7] or +[7]) and is connected to a N-wide signal. Based on IEEE the bits will +likely be backwards from what you expect (i.e. cell [0] will connect to +signal bit [N-1] not bit [0]). + Ignoring this warning will only suppress the lint check, it will simulate correctly. diff --git a/src/V3Inst.cpp b/src/V3Inst.cpp index be2df4f7d..29a06ce10 100644 --- a/src/V3Inst.cpp +++ b/src/V3Inst.cpp @@ -350,6 +350,10 @@ private: // NOP: Arrayed instants: widths match so connect to each instance } else if (expwidth == pinwidth*m_cellRangep->elementsConst()) { // Arrayed instants: one bit for each of the instants (each assign is 1 pinwidth wide) + if (m_cellRangep->littleEndian()) { + nodep->v3warn(LITENDIAN,"Little endian cell range connecting to vector: MSB < LSB of cell range: " + <lsbConst()<<":"<msbConst()); + } AstNode* exprp = nodep->exprp()->unlinkFrBack(); bool inputPin = nodep->modVarp()->isInput(); if (!inputPin && !exprp->castVarRef() diff --git a/src/V3Width.cpp b/src/V3Width.cpp index 84fdc7a95..6c63e972a 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -539,7 +539,8 @@ private: int width = nodep->elementsConst(); if (width > (1<<28)) nodep->v3error("Width of bit range is huge; vector of over 1billion bits: 0x"<littleEndian() && !nodep->backp()->castUnpackArrayDType()) { + if (nodep->littleEndian() && !nodep->backp()->castUnpackArrayDType() + && !nodep->backp()->castCell()) { // For cells we warn in V3Inst nodep->v3warn(LITENDIAN,"Little bit endian vector: MSB < LSB of bit range: "<lsbConst()<<":"<msbConst()); } } diff --git a/test_regress/t/t_interface_array_nocolon.v b/test_regress/t/t_interface_array_nocolon.v index db1289682..a30690af0 100644 --- a/test_regress/t/t_interface_array_nocolon.v +++ b/test_regress/t/t_interface_array_nocolon.v @@ -21,7 +21,12 @@ module t (); wire [2:0] X = 3'b110; - // Should not cause LITENDIAN warning? + // Should not cause LITENDIAN warning, as no harm in array selections. + // verilator lint_on LITENDIAN + foo_intf foo1 [N] (.x(1'b1)); + foo_subm sub1 [N] (.x(1'b1)); + + // Will cause LITENDIAN warning? // verilator lint_off LITENDIAN foo_intf foos [N] (.x(X)); foo_intf fool [1:3] (.x(X)); diff --git a/test_regress/t/t_interface_array_nocolon_bad.pl b/test_regress/t/t_interface_array_nocolon_bad.pl new file mode 100755 index 000000000..75a5f7cc4 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon_bad.pl @@ -0,0 +1,23 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2003 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +compile ( + v_flags2 => ["--lint-only"], + fails=>$Self->{v3}, + expect=> +q{%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:\d+: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 +%Warning-LITENDIAN: Use [^\n]+ +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:\d+: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:\d+: Little endian cell range connecting to vector: MSB < LSB of cell range: 0:2 +%Warning-LITENDIAN: t/t_interface_array_nocolon_bad.v:\d+: Little endian cell range connecting to vector: MSB < LSB of cell range: 1:3 +%Error: Exiting due to}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_interface_array_nocolon_bad.v b/test_regress/t/t_interface_array_nocolon_bad.v new file mode 100644 index 000000000..0056d5d34 --- /dev/null +++ b/test_regress/t/t_interface_array_nocolon_bad.v @@ -0,0 +1,32 @@ +// DESCRIPTION: Verilator: Functionally demonstrate an array of interfaces +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2017 by Mike Popoloski. + +interface foo_intf + ( + input x + ); +endinterface + +module foo_subm + ( + input x + ); +endmodule + +module t (); + + localparam N = 3; + + wire [2:0] X = 3'b110; + + // Will cause LITENDIAN warning? + foo_intf foos [N] (.x(X)); // bad + foo_intf fool [1:3] (.x(X)); // bad + foo_intf foom [3:1] (.x(X)); // ok + + foo_subm subs [N] (.x(X)); // bad + foo_subm subl [1:3] (.x(X)); // bad + foo_subm subm [3:1] (.x(X)); // ok +endmodule