forked from github/verilator
Tests
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@ -24,6 +24,10 @@ module t (/*AUTOARG*/
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integer cnt = 0;
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integer cnt = 0;
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// msg926
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logic [3:0][31:0] packedArray;
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initial packedArray <= '0;
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// event counter
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// event counter
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always @ (posedge clk) begin
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always @ (posedge clk) begin
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cnt <= cnt + 1;
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cnt <= cnt + 1;
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