forked from github/verilator
parent
be26e8da1b
commit
8a85cedaf5
@ -7,24 +7,15 @@ module Vt_debug_emitv_t;
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???? // ENUMITEM 'ZERO'
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32'h0
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???? // ENUMITEM 'ONE'
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32'h1
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???? // REFDTYPE 'e_t'
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struct packed
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{
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???? // REFDTYPE 'e_t'
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a}signed logic [2:0] struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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32'h1signed int [31:0] struct packed
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{signed int [31:0] a;}signed logic [2:0] struct
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{signed logic [2:0] a;}logicunion
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{logic a;}struct packed
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{signed int [31:0] a;}bit [31:0] const struct packed
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{signed int [31:0] a;}const struct packed
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{signed int [31:0] a;}[0:2]struct
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{signed logic [2:0] a;}union
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{logic a;}signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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@ -34,21 +25,14 @@ module Vt_debug_emitv_t;
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] bit [0:0] logic [0:0] e_t;
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typedef struct packed
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{
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???? // REFDTYPE 'e_t'
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a}signed logic [2:0] struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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{signed int [31:0] a;}signed logic [2:0] struct
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{signed logic [2:0] a;}logicunion
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{logic a;}struct packed
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{signed int [31:0] a;}bit [31:0] const struct packed
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{signed int [31:0] a;}const struct packed
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{signed int [31:0] a;}[0:2]struct
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{signed logic [2:0] a;}union
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{logic a;}signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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@ -58,18 +42,13 @@ module Vt_debug_emitv_t;
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] bit [0:0] logic [0:0] ps_t;
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typedef struct
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{signed logic [2:0] a}logicunion
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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{signed logic [2:0] a;}logicunion
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{logic a;}struct packed
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{signed int [31:0] a;}bit [31:0] const struct packed
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{signed int [31:0] a;}const struct packed
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{signed int [31:0] a;}[0:2]struct
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{signed logic [2:0] a;}union
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{logic a;}signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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@ -79,17 +58,12 @@ module Vt_debug_emitv_t;
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] bit [0:0] logic [0:0] us_t;
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typedef union
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{logic a}
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???? // REFDTYPE 'ps_t'
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bit [31:0] const
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???? // REFDTYPE 'ps_t'
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const
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???? // REFDTYPE 'ps_t'
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[0:2]
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???? // REFDTYPE 'us_t'
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???? // REFDTYPE 'union_t'
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signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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{logic a;}struct packed
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{signed int [31:0] a;}bit [31:0] const struct packed
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{signed int [31:0] a;}const struct packed
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{signed int [31:0] a;}[0:2]struct
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{signed logic [2:0] a;}union
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{logic a;}signed int [31:0] signed int [31:0] [0:2]logic [15:0] logic [15:0] logic [15:0] signed int [31:0] signed int [31:0] signed int [31:0]
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???? // QUEUEDTYPE
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signed int [31:0] string
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???? // ASSOCARRAYDTYPE
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@ -99,13 +73,11 @@ module Vt_debug_emitv_t;
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???? // DYNARRAYDTYPE
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signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed int [31:0] signed realstringIData [31:0] signed logic [31:0] signed int [31:0] bit [0:0] logic [0:0] union_t;
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struct packed
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{
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???? // REFDTYPE 'e_t'
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a} ps[0:2];
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{signed int [31:0] a;} ps[0:2];
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struct
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{signed logic [2:0] a} us;
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{signed logic [2:0] a;} us;
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union
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{logic a} unu;
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{logic a;} unu;
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signed int [31:0] array[0:2];
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initial begin
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array = '{0:32'sh1, 1:32'sh2, 2:32'sh3};
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