forked from github/verilator
Tests: Add tagged union test
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@ -2134,7 +2134,9 @@ data_typeVirtual<nodeDTypep>: // ==IEEE: data_type after yVIRTUAL [ yI
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data_type_or_void<nodeDTypep>: // ==IEEE: data_type_or_void
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data_type_or_void<nodeDTypep>: // ==IEEE: data_type_or_void
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data_type { $$ = $1; }
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data_type { $$ = $1; }
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//UNSUP yVOID { UNSUP } // No yTAGGED structures
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| yVOID
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{ $$ = new AstBasicDType{$1, LOGIC_IMPLICIT};
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BBUNSUP($1, "Unsupported: void (for tagged unions)"); }
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;
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;
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var_data_type<nodeDTypep>: // ==IEEE: var_data_type
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var_data_type<nodeDTypep>: // ==IEEE: var_data_type
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68
test_regress/t/t_tagged.out
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68
test_regress/t/t_tagged.out
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@ -0,0 +1,68 @@
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%Error-UNSUPPORTED: t/t_tagged.v:9:18: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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9 | typedef union tagged {
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| ^~~~~~
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... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
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%Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions)
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10 | void m_invalid;
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| ^~~~
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%Error-UNSUPPORTED: t/t_tagged.v:18:11: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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18 | u = tagged m_invalid;
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:21:16: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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21 | case (u) matches
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:22:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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22 | tagged m_invalid: ;
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:23:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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23 | tagged m_int: $stop;
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:26:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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26 | if (u matches tagged m_invalid) ;
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:26:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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26 | if (u matches tagged m_invalid) ;
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| ^~~~~~
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%Error: t/t_tagged.v:26:28: syntax error, unexpected IDENTIFIER
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26 | if (u matches tagged m_invalid) ;
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| ^~~~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:27:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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27 | if (u matches tagged m_int .n) $stop;
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:27:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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27 | if (u matches tagged m_int .n) $stop;
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| ^~~~~~
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%Error: t/t_tagged.v:27:28: syntax error, unexpected IDENTIFIER
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27 | if (u matches tagged m_int .n) $stop;
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| ^~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:29:11: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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29 | u = tagged m_int (123);
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:32:16: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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32 | case (u) matches
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:33:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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33 | tagged m_invalid: $stop;
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:34:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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34 | tagged m_int .n: if (n !== 123) $stop;
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| ^~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:37:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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37 | if (u matches tagged m_invalid) $stop;
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:37:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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37 | if (u matches tagged m_invalid) $stop;
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| ^~~~~~
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%Error: t/t_tagged.v:37:28: syntax error, unexpected IDENTIFIER
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37 | if (u matches tagged m_invalid) $stop;
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| ^~~~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:38:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
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38 | if (u matches tagged m_int .n) if (n != 123) $stop;
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| ^~~~~~~
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%Error-UNSUPPORTED: t/t_tagged.v:38:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
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38 | if (u matches tagged m_int .n) if (n != 123) $stop;
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| ^~~~~~
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%Error: t/t_tagged.v:38:28: syntax error, unexpected IDENTIFIER
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38 | if (u matches tagged m_int .n) if (n != 123) $stop;
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| ^~~~~
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%Error: Exiting due to
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19
test_regress/t/t_tagged.pl
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19
test_regress/t/t_tagged.pl
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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44
test_regress/t/t_tagged.v
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44
test_regress/t/t_tagged.v
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2023 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/);
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typedef union tagged {
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void m_invalid;
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int m_int;
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} u_t;
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u_t u;
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string s;
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initial begin
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u = tagged m_invalid;
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s = $sformatf("%p", u);
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$display("%s e.g. '{tagged m_invalid:void}", s);
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case (u) matches
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tagged m_invalid: ;
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tagged m_int: $stop;
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default: $stop;
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endcase
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if (u matches tagged m_invalid) ;
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if (u matches tagged m_int .n) $stop;
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u = tagged m_int (123);
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s = $sformatf("%p", u);
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$display("'%s e.g. '{tagged m_int:123}", s);
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case (u) matches
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tagged m_invalid: $stop;
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tagged m_int .n: if (n !== 123) $stop;
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default: $stop;
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endcase
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if (u matches tagged m_invalid) $stop;
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if (u matches tagged m_int .n) if (n != 123) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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end
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endmodule
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