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Tests: Add tagged union test

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This commit is contained in:
Wilson Snyder 2023-03-02 08:11:11 -05:00
parent 3df29085c8
commit 8a5804fc3a
4 changed files with 134 additions and 1 deletions
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4
src/verilog.y
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@ -2134,7 +2134,9 @@ data_typeVirtual<nodeDTypep>: // ==IEEE: data_type after yVIRTUAL [ yI
data_type_or_void<nodeDTypep>: // ==IEEE: data_type_or_void
data_type { $$ = $1; }
//UNSUP yVOID { UNSUP } // No yTAGGED structures
| yVOID
{ $$ = new AstBasicDType{$1, LOGIC_IMPLICIT};
BBUNSUP($1, "Unsupported: void (for tagged unions)"); }
;
var_data_type<nodeDTypep>: // ==IEEE: var_data_type

68
test_regress/t/t_tagged.out Normal file
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@ -0,0 +1,68 @@
%Error-UNSUPPORTED: t/t_tagged.v:9:18: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
9 | typedef union tagged {
| ^~~~~~
... For error description see https://verilator.org/warn/UNSUPPORTED?v=latest
%Error-UNSUPPORTED: t/t_tagged.v:10:6: Unsupported: void (for tagged unions)
10 | void m_invalid;
| ^~~~
%Error-UNSUPPORTED: t/t_tagged.v:18:11: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
18 | u = tagged m_invalid;
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:21:16: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
21 | case (u) matches
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:22:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
22 | tagged m_invalid: ;
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:23:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
23 | tagged m_int: $stop;
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:26:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
26 | if (u matches tagged m_invalid) ;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:26:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
26 | if (u matches tagged m_invalid) ;
| ^~~~~~
%Error: t/t_tagged.v:26:28: syntax error, unexpected IDENTIFIER
26 | if (u matches tagged m_invalid) ;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:27:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
27 | if (u matches tagged m_int .n) $stop;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:27:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
27 | if (u matches tagged m_int .n) $stop;
| ^~~~~~
%Error: t/t_tagged.v:27:28: syntax error, unexpected IDENTIFIER
27 | if (u matches tagged m_int .n) $stop;
| ^~~~~
%Error-UNSUPPORTED: t/t_tagged.v:29:11: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
29 | u = tagged m_int (123);
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:32:16: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
32 | case (u) matches
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:33:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
33 | tagged m_invalid: $stop;
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:34:9: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
34 | tagged m_int .n: if (n !== 123) $stop;
| ^~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:37:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
37 | if (u matches tagged m_invalid) $stop;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:37:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
37 | if (u matches tagged m_invalid) $stop;
| ^~~~~~
%Error: t/t_tagged.v:37:28: syntax error, unexpected IDENTIFIER
37 | if (u matches tagged m_invalid) $stop;
| ^~~~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:38:13: Unsupported: SystemVerilog 2005 reserved word not implemented: 'matches'
38 | if (u matches tagged m_int .n) if (n != 123) $stop;
| ^~~~~~~
%Error-UNSUPPORTED: t/t_tagged.v:38:21: Unsupported: SystemVerilog 2005 reserved word not implemented: 'tagged'
38 | if (u matches tagged m_int .n) if (n != 123) $stop;
| ^~~~~~
%Error: t/t_tagged.v:38:28: syntax error, unexpected IDENTIFIER
38 | if (u matches tagged m_int .n) if (n != 123) $stop;
| ^~~~~
%Error: Exiting due to

19
test_regress/t/t_tagged.pl Executable file
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@ -0,0 +1,19 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
fails => $Self->{vlt_all},
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

44
test_regress/t/t_tagged.v Normal file
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@ -0,0 +1,44 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2023 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/);
typedef union tagged {
void m_invalid;
int m_int;
} u_t;
u_t u;
string s;
initial begin
u = tagged m_invalid;
s = $sformatf("%p", u);
$display("%s e.g. '{tagged m_invalid:void}", s);
case (u) matches
tagged m_invalid: ;
tagged m_int: $stop;
default: $stop;
endcase
if (u matches tagged m_invalid) ;
if (u matches tagged m_int .n) $stop;
u = tagged m_int (123);
s = $sformatf("%p", u);
$display("'%s e.g. '{tagged m_int:123}", s);
case (u) matches
tagged m_invalid: $stop;
tagged m_int .n: if (n !== 123) $stop;
default: $stop;
endcase
if (u matches tagged m_invalid) $stop;
if (u matches tagged m_int .n) if (n != 123) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule