Fix LITENDIAN on unpacked structures, bug614.

Changes

@@ -7,6 +7,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix DETECTARRAY on packed structures, bug610. [Jeremy Bennett]
 
+****  Fix LITENDIAN on unpacked structures, bug614. [Wai Sum Mong]
+
 ****  Fix 32-bit OS VPI scan issue, bug615.  [Jeremy Bennett, Rich Porter]
 
 

bin/verilator

@@ -2927,7 +2927,7 @@ simulators.
 
 =item LITENDIAN
 
-Warns that a vector is declared with little endian bit numbering
+Warns that a packed vector is declared with little endian bit numbering
 (i.e. [0:7]).  Big endian bit numbering is now the overwhelming standard,
 and little numbering is now thus often due to simple oversight instead of
 intent.

src/V3Width.cpp

@@ -386,7 +386,7 @@ private:
 	    int width = nodep->elementsConst();
 	    if (width > (1<<28)) nodep->v3error("Width of bit range is huge; vector of over 1billion bits: 0x"<<hex<<width);
 	    // Note width() not set on range; use elementsConst()
-	    if (nodep->littleEndian()) {
+	    if (nodep->littleEndian() && !nodep->backp()->castUnpackArrayDType()) {
 		nodep->v3warn(LITENDIAN,"Little bit endian vector: MSB < LSB of bit range: "<<nodep->lsbConst()<<":"<<nodep->msbConst());
 	    }
 	}

test_regress/t/t_select_little_pack.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_select_little_pack.v

@@ -0,0 +1,28 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2009 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   // No endian warning here
+   wire [7:0] 	pack [3:0];
+
+   initial begin
+      pack[0] = 8'h78;
+      pack[1] = 8'h88;
+      pack[2] = 8'h98;
+      pack[3] = 8'hA8;
+      if (pack[0] !== 8'h78) $stop;
+      if (pack[1] !== 8'h88) $stop;
+      if (pack[2] !== 8'h98) $stop;
+      if (pack[3] !== 8'hA8) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule