Partial fix to avoid init error on lint-only (#2895)

This commit is contained in:
Wilson Snyder 2021-04-24 09:44:00 -04:00
parent 82b878ce42
commit 8749f545b6
3 changed files with 51 additions and 1 deletions

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@ -1266,7 +1266,9 @@ public:
virtual void visit(AstNode* nodep) override {
puts(string("\n???? // ") + nodep->prettyTypeName() + "\n");
iterateChildren(nodep);
nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName());
if (!v3Global.opt.lintOnly()) { // An internal problem, so suppress
nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName());
}
}
EmitCStmts() {

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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
# TODO change to compile()
lint(
);
# No execute, not self-checking
ok(1);
1;

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@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2020 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
package pkg;
localparam string REGS [0:31]
= '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
"s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6",
"fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
"ft10", "ft11"};
function string disasm32(logic [4:0] op);
return $sformatf("lui %s" , REGS[op]);
endfunction
endpackage
module t(/*AUTOARG*/
// Inputs
op
);
import pkg::*;
input [4:0] op;
always_comb begin
$display("OP: 0x%08x: %s", op, disasm32(op));
end
endmodule