forked from github/verilator
Partial fix to avoid init error on lint-only (#2895)
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@ -1266,7 +1266,9 @@ public:
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virtual void visit(AstNode* nodep) override {
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puts(string("\n???? // ") + nodep->prettyTypeName() + "\n");
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iterateChildren(nodep);
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nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName());
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if (!v3Global.opt.lintOnly()) { // An internal problem, so suppress
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nodep->v3fatalSrc("Unknown node type reached emitter: " << nodep->prettyTypeName());
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}
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}
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EmitCStmts() {
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20
test_regress/t/t_unpacked_str_init.pl
Executable file
20
test_regress/t/t_unpacked_str_init.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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# TODO change to compile()
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lint(
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);
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# No execute, not self-checking
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ok(1);
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1;
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28
test_regress/t/t_unpacked_str_init.v
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28
test_regress/t/t_unpacked_str_init.v
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@ -0,0 +1,28 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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package pkg;
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localparam string REGS [0:31]
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= '{"zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2",
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"s0/fp", "s1", "a0", "a1", "a2", "a3", "a4", "a5",
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"fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6",
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"fs7", "fs8", "fs9", "fs10", "fs11", "ft8", "ft9",
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"ft10", "ft11"};
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function string disasm32(logic [4:0] op);
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return $sformatf("lui %s" , REGS[op]);
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endfunction
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endpackage
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module t(/*AUTOARG*/
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// Inputs
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op
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);
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import pkg::*;
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input [4:0] op;
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always_comb begin
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$display("OP: 0x%08x: %s", op, disasm32(op));
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end
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endmodule
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