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Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type (#3236).

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This commit is contained in:
Wilson Snyder 2021-12-09 19:41:33 -05:00
parent 706162ecc6
commit 8696e38e6f
6 changed files with 62 additions and 7 deletions
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7
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@ -11,10 +11,17 @@ contributors that suggested a given feature are shown in []. Thanks!
Verilator 4.217 devel
==========================
**Major:**
* Primary inputs and outputs (VL_INW/VL_OUTW) now use VlWide type.
In general this should be backward compatible, but may lead to some
wrapper code needing changes.
**Minor:**
* Fix MSWIN compile error (#2681). [Unai Martinez-Corral]
* Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235)
* Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle]
Verilator 4.216 2021-12-05

8
include/verilated_types.h
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@ -45,22 +45,22 @@ extern std::string VL_TO_STRING_W(int words, const WDataInP obj);
#define VL_SIG16(name, msb, lsb) SData name ///< Declare signal, 9-16 bits
#define VL_SIG64(name, msb, lsb) QData name ///< Declare signal, 33-64 bits
#define VL_SIG(name, msb, lsb) IData name ///< Declare signal, 17-32 bits
#define VL_SIGW(name, msb, lsb, words) WData name[words] ///< Declare signal, 65+ bits
#define VL_SIGW(name, msb, lsb, words) VlWide<words> name ///< Declare signal, 65+ bits
#define VL_IN8(name, msb, lsb) CData name ///< Declare input signal, 1-8 bits
#define VL_IN16(name, msb, lsb) SData name ///< Declare input signal, 9-16 bits
#define VL_IN64(name, msb, lsb) QData name ///< Declare input signal, 33-64 bits
#define VL_IN(name, msb, lsb) IData name ///< Declare input signal, 17-32 bits
#define VL_INW(name, msb, lsb, words) WData name[words] ///< Declare input signal, 65+ bits
#define VL_INW(name, msb, lsb, words) VlWide<words> name ///< Declare input signal, 65+ bits
#define VL_INOUT8(name, msb, lsb) CData name ///< Declare bidir signal, 1-8 bits
#define VL_INOUT16(name, msb, lsb) SData name ///< Declare bidir signal, 9-16 bits
#define VL_INOUT64(name, msb, lsb) QData name ///< Declare bidir signal, 33-64 bits
#define VL_INOUT(name, msb, lsb) IData name ///< Declare bidir signal, 17-32 bits
#define VL_INOUTW(name, msb, lsb, words) WData name[words] ///< Declare bidir signal, 65+ bits
#define VL_INOUTW(name, msb, lsb, words) VlWide<words> name ///< Declare bidir signal, 65+ bits
#define VL_OUT8(name, msb, lsb) CData name ///< Declare output signal, 1-8 bits
#define VL_OUT16(name, msb, lsb) SData name ///< Declare output signal, 9-16 bits
#define VL_OUT64(name, msb, lsb) QData name ///< Declare output signal, 33-64bits
#define VL_OUT(name, msb, lsb) IData name ///< Declare output signal, 17-32 bits
#define VL_OUTW(name, msb, lsb, words) WData name[words] ///< Declare output signal, 65+ bits
#define VL_OUTW(name, msb, lsb, words) VlWide<words> name ///< Declare output signal, 65+ bits
//===================================================================
// Shuffle RNG

1
src/V3EmitCBase.cpp
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@ -184,7 +184,6 @@ void EmitCBaseVisitor::emitVarDecl(const AstVar* nodep, bool asRef) {
puts("16");
} else if (nodep->isWide()) {
puts("W");
refNeedParens = true;
}
puts("(");

21
test_regress/t/t_display_io.pl Executable file
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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2021 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(simulator => 1);
compile(
);
execute(
check_finished => 1,
);
ok(1);
1;

28
test_regress/t/t_display_io.v Normal file
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@ -0,0 +1,28 @@
// DESCRIPTION: Verilator: $display() test for %l
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2021 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t(/*AUTOARG*/
// Outputs
o,
// Inputs
i
);
input logic [95:0] i;
output logic [95:0] o;
string a_s;
initial begin
o = ~i;
$sformat(a_s, "%h", i);
$display(a_s);
$sformat(a_s, "%h", o);
$display(a_s);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule

4
test_regress/t/t_var_pins_cc.pl
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@ -25,14 +25,14 @@ compile(
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN16 \(&i16,15,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN \(&i32,31,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_IN64 \(&i64,63,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(\(&i65\),64,0,3\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_INW \(&i65,64,0,3\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o1,0,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT8 \(&o8,7,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT16\(&o16,15,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT \(&o32,31,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUT64\(&o64,63,0\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(\(&o65\),64,0,3\);/x);
file_grep("$Self->{obj_dir}/Vt_var_pins_cc.h", qr/VL_OUTW \(&o65,64,0,3\);/x);
}
ok(1);