From 85d790ff79d129b2f11b707cd2d1b28125ed360c Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Sat, 8 Mar 2014 13:33:44 -0500
Subject: [PATCH] Fix inside statement EQWILD error, bug718.

---
 Changes                         |  2 +
 src/V3Tristate.cpp              | 14 ++++++
 test_regress/t/t_inside_wild.pl | 18 +++++++
 test_regress/t/t_inside_wild.v  | 83 +++++++++++++++++++++++++++++++++
 4 files changed, 117 insertions(+)
 create mode 100755 test_regress/t/t_inside_wild.pl
 create mode 100644 test_regress/t/t_inside_wild.v

diff --git a/Changes b/Changes
index a60586559..0cca4c5a1 100644
--- a/Changes
+++ b/Changes
@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix internal error on "input x =" syntax error, bug716. [Lane Brooks]
 
+****  Fix inside statement EQWILD error, bug718. [Jan Egil Ruud]
+
 
 * Verilator 3.855 2014-01-18
 
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 882548c07..ade9d41f8 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -957,12 +957,26 @@ class TristateVisitor : public TristateBaseVisitor {
 	    }
 	}
     }
+    void visitEqNeqWild(AstNodeBiop* nodep) {
+	if (!nodep->rhsp()->castConst()) {
+	    nodep->v3error("Unsupported: RHS of ==? or !=? must be constant to be synthesizable");  // Says spec.
+	    // rhs we want to keep X/Z intact, so otherwise ignore
+	}
+	nodep->lhsp()->iterateAndNext(*this);
+	if (nodep->lhsp()->user1p()) { nodep->v3error("Unsupported LHS tristate construct: "<<nodep->prettyTypeName()); return; }
+    }
     virtual void visit(AstEqCase* nodep, AstNUser*) {
 	visitCaseEq(nodep,false);
     }
     virtual void visit(AstNeqCase* nodep, AstNUser*) {
 	visitCaseEq(nodep,true);
     }
+    virtual void visit(AstEqWild* nodep, AstNUser*) {
+	visitEqNeqWild(nodep);
+    }
+    virtual void visit(AstNeqWild* nodep, AstNUser*) {
+	visitEqNeqWild(nodep);
+    }
 
     virtual void visit(AstPull* nodep, AstNUser*) {
 	UINFO(9,dbgState()<<nodep<<endl);
diff --git a/test_regress/t/t_inside_wild.pl b/test_regress/t/t_inside_wild.pl
new file mode 100755
index 000000000..f91289753
--- /dev/null
+++ b/test_regress/t/t_inside_wild.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_inside_wild.v b/test_regress/t/t_inside_wild.v
new file mode 100644
index 000000000..d0ed5f3c7
--- /dev/null
+++ b/test_regress/t/t_inside_wild.v
@@ -0,0 +1,83 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   wire [4:0] in = crc[4:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   logic		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[4:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {63'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+	 sum <= 64'h0;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 // What checksum will we end up with (above print should match)
+`define EXPECTED_SUM 64'h7a7bd4ee927e7cc3
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   //bug718
+
+   input clk;
+
+   input logic [4:0] in;
+
+   output logic out;
+
+   always @(posedge clk) begin
+      out <= in inside {5'b1_1?1?};
+   end
+
+endmodule // t
\ No newline at end of file