Add --top option as alias of --top-module.

Changes

@@ -5,6 +5,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 * Verilator 4.107 devel
 
+***   Add --top option as alias of --top-module.
+
 ****  Fix passing parameter type instantiations by position number.
 
 

bin/verilator

@@ -409,6 +409,7 @@ arguments.
     --threads-max-mtasks <mtasks>  Tune maximum mtask partitioning
     --timescale <timescale>     Sets default timescale
     --timescale-override <timescale>  Overrides all timescales
+    --top <topname>             Alias of --top-module
     --top-module <topname>      Name of top level input module
     --trace                     Enable waveform creation
     --trace-coverage            Enable tracing of coverage
@@ -1260,8 +1261,8 @@ With -E, show comments in preprocessor output.
 =item --prefix I<topname>
 
 Specifies the name of the top level class and makefile.  Defaults to V
-prepended to the name of the --top-module switch, or V prepended to the
-first Verilog filename passed on the command line.
+prepended to the name of the --top switch, or V prepended to the first
+Verilog filename passed on the command line.
 
 =item --prof-cfuncs
 
@@ -1523,6 +1524,8 @@ sc_set_time_resolution, or the C++ code instantiating the Verilated module.
 As 1fs is the finest time precision it may be desirable to always use a
 precision of 1fs.
 
+=item --top I<topname>
+
 =item --top-module I<topname>
 
 When the input Verilog contains more than one top level module, specifies
@@ -4628,10 +4631,10 @@ automatically resolved by having filenames that match the module names.
 
 2. A single module is intended to be the top, the name of it is known, and
 all other modules should be ignored if not part of the design.  The best
-solution is to use the --top-module option to specify the top module's
-name. All other modules that are not part of the design will be for the
-most part ignored (they must be clean in syntax and their contents will be
-removed as part of the Verilog module elaboration process.)
+solution is to use the --top option to specify the top module's name. All
+other modules that are not part of the design will be for the most part
+ignored (they must be clean in syntax and their contents will be removed as
+part of the Verilog module elaboration process.)
 
 3. Multiple modules are intended to be design tops, e.g. when linting a
 library file.  As multiple modules are desired, disable the MULTITOP

src/V3Options.cpp

@@ -1502,7 +1502,7 @@ void V3Options::parseOptsList(FileLine* fl, const string& optdir, int argc, char
                     m_timeDefaultPrec = prec;
                     m_timeOverridePrec = prec;
                 }
-            } else if (!strcmp(sw, "-top-module") && (i + 1) < argc) {
+            } else if ((!strcmp(sw, "-top-module") || !strcmp(sw, "-top")) && (i + 1) < argc) {
                 shift;
                 m_topModule = argv[i];
             } else if (!strcmp(sw, "-unused-regexp") && (i + 1) < argc) {

test_regress/t/t_flag_topmodule_inline.pl

@@ -11,7 +11,8 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
 scenarios(vlt => 1);
 
 compile(
-    v_flags2 => ["--top-module b"],
+    # This also tests --top as opposed to --top-module
+    v_flags2 => ["--top b"],
     );
 
 execute(

verilator-config.cmake.in

@@ -129,7 +129,7 @@ function(verilate TARGET)
   endif()
 
   if (VERILATE_TOP_MODULE)
-    list(APPEND VERILATOR_ARGS --top-module ${VERILATE_TOP_MODULE})
+    list(APPEND VERILATOR_ARGS --top ${VERILATE_TOP_MODULE})
   endif()
 
   if (VERILATE_THREADS)