diff --git a/Changes b/Changes index 91edd22a8..28fc047ca 100644 --- a/Changes +++ b/Changes @@ -31,6 +31,8 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix tracing empty sc module (#2729). +**** Fix generate for unrolling to be signed (#2730). [yanx21] + * Verilator 4.106 2020-12-02 diff --git a/src/V3Number.h b/src/V3Number.h index e681069bf..47ca60a11 100644 --- a/src/V3Number.h +++ b/src/V3Number.h @@ -198,6 +198,7 @@ private: void V3NumberCreate(AstNode* nodep, const char* sourcep, FileLine* fl); void init(AstNode* nodep, int swidth, bool sized = true) { setNames(nodep); + // dtype info does NOT from nodep's dtype; nodep only for error reporting m_signed = false; m_double = false; m_isNull = false; @@ -205,7 +206,7 @@ private: m_autoExtend = false; m_fromString = false; width(swidth, sized); - for (int i = 0; i < words(); i++) m_value[i] = m_valueX[i] = 0; + for (int i = 0; i < words(); ++i) m_value[i] = m_valueX[i] = 0; } void setNames(AstNode* nodep); static string displayPad(size_t fmtsize, char pad, bool left, const string& in); diff --git a/src/V3Param.cpp b/src/V3Param.cpp index 37597d418..7cced105d 100644 --- a/src/V3Param.cpp +++ b/src/V3Param.cpp @@ -502,6 +502,7 @@ class ParamProcessor final { // Remove any existing parameter if (modvarp->valuep()) modvarp->valuep()->unlinkFrBack()->deleteTree(); // Set this parameter to value requested by cell + UINFO(9, " set param " << modvarp << " = " << newp << endl); modvarp->valuep(newp->cloneTree(false)); modvarp->overriddenParam(true); } else if (AstParamTypeDType* modptp = pinp->modPTypep()) { diff --git a/src/V3Unroll.cpp b/src/V3Unroll.cpp index ffa92b5f1..28b96f230 100644 --- a/src/V3Unroll.cpp +++ b/src/V3Unroll.cpp @@ -230,6 +230,7 @@ private: AstConst new_con(clonep->fileline(), *res); new_con.dtypeFrom(dtypep); outNum = new_con.num(); + outNum.isSigned(dtypep->isSigned()); VL_DO_DANGLING(clonep->deleteTree(), clonep); return true; } diff --git a/test_regress/t/t_generate_fatal_bad.out b/test_regress/t/t_generate_fatal_bad.out index 0a0bc2a9b..c23052748 100644 --- a/test_regress/t/t_generate_fatal_bad.out +++ b/test_regress/t/t_generate_fatal_bad.out @@ -1,7 +1,7 @@ %Warning-USERFATAL: "boom" ... Use "/* verilator lint_off USERFATAL */" and lint_on around source to disable this message. %Error: t/t_generate_fatal_bad.v:13:29: Expecting expression to be constant, but can't determine constant for FUNCREF 'get_baz' - : ... In instance t.genloop[0].foo_inst + : ... In instance t.nested_loop[10].foo2_inst.foo2_loop[1].foo_in_foo2_inst t/t_generate_fatal_bad.v:9:4: ... Location of non-constant STOP: $stop executed during function constification; maybe indicates assertion firing t/t_generate_fatal_bad.v:13:29: ... Called from get_baz() with parameters: bar = ?32?h0 diff --git a/test_regress/t/t_genfor_signed.out b/test_regress/t/t_genfor_signed.out new file mode 100644 index 000000000..7f921d5a9 --- /dev/null +++ b/test_regress/t/t_genfor_signed.out @@ -0,0 +1,9 @@ +top.t.u_sub1.unnamedblk1 1..1 i=1 +top.t.u_sub0.unnamedblk1 1..0 i=1 +top.t.u_sub0.unnamedblk1 1..0 i=0 +top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=1 +top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=0 +top.t.SUB_PIPE[-1].u_sub.unnamedblk1 1..-1 i=-1 +top.t.SUB_PIPE[0].u_sub.unnamedblk1 1..0 i=1 +top.t.SUB_PIPE[0].u_sub.unnamedblk1 1..0 i=0 +*-* All Finished *-* diff --git a/test_regress/t/t_genfor_signed.pl b/test_regress/t/t_genfor_signed.pl new file mode 100755 index 000000000..c6a015747 --- /dev/null +++ b/test_regress/t/t_genfor_signed.pl @@ -0,0 +1,22 @@ +#!/usr/bin/env perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2019 by Wilson Snyder. This program is free software; you +# can redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. +# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0 + +scenarios(simulator => 1); + +compile( + ); + +execute( + check_finished => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_genfor_signed.v b/test_regress/t/t_genfor_signed.v new file mode 100644 index 000000000..e79d64bac --- /dev/null +++ b/test_regress/t/t_genfor_signed.v @@ -0,0 +1,64 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// Use this file as a template for submitting bugs, etc. +// This module takes a single clock input, and should either +// $write("*-* All Finished *-*\n"); +// $finish; +// on success, or $stop. +// +// The code as shown applies a random vector to the Test +// module, then calculates a CRC on the Test module's outputs. +// +// **If you do not wish for your code to be released to the public +// please note it here, otherwise:** +// +// This file ONLY is placed under the Creative Commons Public Domain, for +// any use, without warranty, 2020 by ____YOUR_NAME_HERE____. +// SPDX-License-Identifier: CC0-1.0 + +module t # + ( + parameter PIPE = 4 + )(/*AUTOARG*/ + // Inputs + clk + ); + + input clk; + + // These are ok + sub #( + .P_STOP (1) + ) u_sub1 (); + sub #( + .P_STOP (0) + ) u_sub0 (); + + genvar i; + for (i = -1; i < 1; i++) begin: SUB_PIPE + sub #( + .P_STOP (i) + ) u_sub (); + end + + always @ (posedge clk) begin + $write("*-* All Finished *-*\n"); + $finish; + end + +endmodule + +module sub # + ( + parameter P_START = 1, + parameter P_STOP = 0 + )( + ); + + initial begin + for (int i = P_START; i >= P_STOP; --i) begin + $display("%m %0d..%0d i=%0d", P_START, P_STOP, i); + end + end + +endmodule diff --git a/test_regress/t/t_lint_width_genfor_bad.out b/test_regress/t/t_lint_width_genfor_bad.out index 5e344a696..a814e38a8 100644 --- a/test_regress/t/t_lint_width_genfor_bad.out +++ b/test_regress/t/t_lint_width_genfor_bad.out @@ -1,4 +1,4 @@ -%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?h10' generates 32 or 5 bits. +%Warning-WIDTH: t/t_lint_width_genfor_bad.v:25:13: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's CONST '?32?sh10' generates 32 or 5 bits. : ... In instance t 25 | rg = g; | ^