From 80859a609a8d2ce96bede77c43738d3795c9a166 Mon Sep 17 00:00:00 2001 From: Wilson Snyder Date: Sat, 1 Jan 2022 16:48:15 -0500 Subject: [PATCH] Fix $fclose not accepting expressions (#3237). --- Changes | 1 + src/verilog.y | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Changes b/Changes index 674cab1c3..427a10d85 100644 --- a/Changes +++ b/Changes @@ -30,6 +30,7 @@ Verilator 4.217 devel * Fix VL_STREAML_FAST_QQI with 64 bit left-hand-side (#3232) (#3235) * Fix $sformat of inputs/outputs (#3236). [Adrien Le Masle] * Fix associative array foreach loop (#3229). +* Fix $fclose not accepting expressions (#3237). [Julie Schwartz] * Fix $random not updating seed (#3238). [Julie Schwartz] * Fix splitting of _eval and other top level functions. [Geza Lore, Shunyao CAD] diff --git a/src/verilog.y b/src/verilog.y index a3f850c3b..f41428ffd 100644 --- a/src/verilog.y +++ b/src/verilog.y @@ -3619,7 +3619,7 @@ system_t_call: // IEEE: system_tf_call (as task) // | yD_EXIT parenE { $$ = new AstFinish($1); } // - | yD_FCLOSE '(' idClassSel ')' { $$ = new AstFClose($1, $3); } + | yD_FCLOSE '(' expr ')' { $$ = new AstFClose{$1, $3}; } | yD_FFLUSH parenE { $$ = new AstFFlush($1, nullptr); } | yD_FFLUSH '(' expr ')' { $$ = new AstFFlush($1, $3); } | yD_FINISH parenE { $$ = new AstFinish($1); }