Tests: Tests to fix misc internal coverage holes.

This commit is contained in:
Wilson Snyder 2020-06-04 20:23:55 -04:00
parent a433096d5a
commit 7fe49de420
20 changed files with 184 additions and 12 deletions

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@ -21,8 +21,8 @@ source_globs("src/*.cpp",
"include/*/*.c",
);
remove_source("/usr/include/*");
remove_source("/usr/lib/*");
# Note *'s are removed when using fastcov
remove_source("/usr/*");
remove_source("*/include/sysc/*");
remove_source("*/V3ClkGater.cpp");
remove_source("*/V3ClkGater.h");
@ -42,6 +42,13 @@ remove_source("*examples/*");
# Would just be removed with remove_source in later step
remove_gcda_regexp(qr!test_regress/.*/(Vt_|Vtop_).*\.gcda!);
exclude_line_regexp(qr/(\bv3fatalSrc\b|\bfatalSrc\b|\bVL_UNCOVERABLE\b|\bVL_FATAL|\bUASSERT|\bERROR_RSVD_WORD\bV3ERROR_NA)/);
exclude_line_regexp(qr/(\bv3fatalSrc\b
|\bfatalSrc\b
|\bVL_UNCOVERABLE\b
|\bVL_FATAL
|\bUASSERT
|\bERROR_RSVD_WORD
|\bV3ERROR_NA
|\bUINFO\b)/x);
1;

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@ -511,7 +511,7 @@ private:
} else if (type == AstCFuncType::TRACE_CHANGE) {
registration += "Chg";
} else {
funcp->v3fatal("Don't know how to register this type of function");
funcp->v3fatalSrc("Don't know how to register this type of function");
}
registration += "Cb(&" + protect(name) + ", __VlSymsp);\n";
AstCStmt* const stmtp = new AstCStmt(flp, registration);

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@ -0,0 +1,2 @@
%Error: Cannot open -f command file: file_will_not_exist.vc
%Error: Exiting due to

20
test_regress/t/t_f_bad.pl Executable file
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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
verilator_flags2 => ["--lint-only -f file_will_not_exist.vc"],
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
scenarios(vlt => 1);
compile(
v_flags2 => ["-f t/t_flag_define.vc"],
v_flags2 => ["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"],
);
execute(

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@ -108,6 +108,16 @@ module t;
$write("%%Error: Missing define\n"); $stop;
`endif
`ifndef CMD_DEF
$write("%%Error: Missing define\n"); $stop;
`endif
`ifndef CMD_DEF2
$write("%%Error: Missing define\n"); $stop;
`endif
`ifdef CMD_UNDEF
$write("%%Error: Extra define\n"); $stop;
`endif
$write("*-* All Finished *-*\n");
$finish;
end

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@ -0,0 +1,2 @@
%Error: --main not usable with SystemC. Suggest see examples for sc_main().
%Error: Exiting due to

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@ -0,0 +1,23 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2019 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
compile(
verilator_flags2 => ['--exe --build --main --sc'],
verilator_make_cmake => 0,
verilator_make_gmake => 0,
make_main => 0,
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1 @@
%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information

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@ -0,0 +1,21 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
run(cmd => ["../bin/verilator --lint-only"],
fails => 1,
logfile => "$Self->{obj_dir}/sim.log",
expect_filename => $Self->{golden_filename},
verilator_run => 1,
);
ok(1);
1;

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@ -48,7 +48,7 @@ compile( # Don't call cmake nor gmake from driver.pl. Just build here
verilator_make_gmake => 0,
verilator_flags2 => ['--exe --cc --build --no-verilate',
'../' . $Self->{main_filename},
'--debugi 1 --dump-tree'],
'--debugi 1 --dump-tree --dump-tree-addrids'],
);
# The previous run must not verilated, only build is expected.

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@ -0,0 +1 @@
%Error: Unknown warning specified: -Werror-NOSUCHERRORASTHIS

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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
top_filename("t/t_flag_werror.v");
lint(
fails => 1,
verilator_flags => [qw(-cc -Werror-NOSUCHERRORASTHIS)],
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1 @@
%Error: Unknown warning specified: -Wno-NOSUCHERRORASTHIS

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@ -0,0 +1,20 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2008 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
lint(
verilator_flags2 => ["--lint-only -Wno-NOSUCHERRORASTHIS"],
fails => 1,
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -0,0 +1 @@
%Error: Unknown warning specified: -Wwarn-NOSUCHERRORASTHIS

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@ -0,0 +1,22 @@
#!/usr/bin/env perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you
# can redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
scenarios(vlt => 1);
top_filename("t/t_flag_werror.v");
lint(
fails => 1,
verilator_flags => [qw(-cc -Wwarn-NOSUCHERRORASTHIS)],
expect_filename => $Self->{golden_filename},
);
ok(1);
1;

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@ -1,10 +1,19 @@
%Error: t/t_func_return_bad.v:10:7: Return isn't underneath a task or function
10 | return;
%Error: t/t_func_return_bad.v:10:7: Return underneath a task shouldn't have return value
10 | return 1;
| ^~~~~~
%Error: t/t_func_return_bad.v:11:7: continue isn't underneath a loop
11 | continue;
%Error: t/t_func_return_bad.v:13:7: Return underneath a function should have return value
13 | return;
| ^~~~~~
%Error: t/t_func_return_bad.v:17:7: Return isn't underneath a task or function
17 | return;
| ^~~~~~
%Error: t/t_func_return_bad.v:18:7: continue isn't underneath a loop
18 | continue;
| ^~~~~~~~
%Error: t/t_func_return_bad.v:12:7: break isn't underneath a loop
12 | break;
%Error: t/t_func_return_bad.v:19:7: break isn't underneath a loop
19 | break;
| ^~~~~
%Error: t/t_func_return_bad.v:22:7: disable isn't underneath a begin with name: 'foo'
22 | disable foo;
| ^~~~~~~
%Error: Exiting due to

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@ -6,9 +6,19 @@
module t (/*AUTOARG*/);
task t1;
return 1; // Shouldn't return value
endtask
function int f1;
return; // Should return value
endfunction
initial begin
return; // Not under function
continue; // Not under loop
break; // Not under loop
begin : foo
end
disable foo; // Disabling outside block
end
endmodule

0
test_regress/t/t_increment_bad.pl Normal file → Executable file
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