forked from github/verilator
Tests: Tests to fix misc internal coverage holes.
This commit is contained in:
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a433096d5a
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7fe49de420
@ -21,8 +21,8 @@ source_globs("src/*.cpp",
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"include/*/*.c",
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);
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remove_source("/usr/include/*");
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remove_source("/usr/lib/*");
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# Note *'s are removed when using fastcov
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remove_source("/usr/*");
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remove_source("*/include/sysc/*");
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remove_source("*/V3ClkGater.cpp");
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remove_source("*/V3ClkGater.h");
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@ -42,6 +42,13 @@ remove_source("*examples/*");
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# Would just be removed with remove_source in later step
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remove_gcda_regexp(qr!test_regress/.*/(Vt_|Vtop_).*\.gcda!);
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exclude_line_regexp(qr/(\bv3fatalSrc\b|\bfatalSrc\b|\bVL_UNCOVERABLE\b|\bVL_FATAL|\bUASSERT|\bERROR_RSVD_WORD\bV3ERROR_NA)/);
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exclude_line_regexp(qr/(\bv3fatalSrc\b
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|\bfatalSrc\b
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|\bVL_UNCOVERABLE\b
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|\bVL_FATAL
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|\bUASSERT
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|\bERROR_RSVD_WORD
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|\bV3ERROR_NA
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|\bUINFO\b)/x);
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1;
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@ -511,7 +511,7 @@ private:
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} else if (type == AstCFuncType::TRACE_CHANGE) {
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registration += "Chg";
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} else {
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funcp->v3fatal("Don't know how to register this type of function");
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funcp->v3fatalSrc("Don't know how to register this type of function");
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}
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registration += "Cb(&" + protect(name) + ", __VlSymsp);\n";
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AstCStmt* const stmtp = new AstCStmt(flp, registration);
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2
test_regress/t/t_f_bad.out
Normal file
2
test_regress/t/t_f_bad.out
Normal file
@ -0,0 +1,2 @@
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%Error: Cannot open -f command file: file_will_not_exist.vc
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%Error: Exiting due to
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20
test_regress/t/t_f_bad.pl
Executable file
20
test_regress/t/t_f_bad.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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verilator_flags2 => ["--lint-only -f file_will_not_exist.vc"],
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -11,7 +11,7 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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scenarios(vlt => 1);
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compile(
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v_flags2 => ["-f t/t_flag_define.vc"],
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v_flags2 => ["-f t/t_flag_define.vc -DCMD_DEF -DCMD_UNDEF -UCMD_UNDEF +define+CMD_DEF2"],
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);
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execute(
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@ -108,6 +108,16 @@ module t;
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifndef CMD_DEF
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifndef CMD_DEF2
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$write("%%Error: Missing define\n"); $stop;
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`endif
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`ifdef CMD_UNDEF
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$write("%%Error: Extra define\n"); $stop;
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`endif
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$write("*-* All Finished *-*\n");
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$finish;
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end
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2
test_regress/t/t_flag_main_sc_bad.out
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2
test_regress/t/t_flag_main_sc_bad.out
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@ -0,0 +1,2 @@
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%Error: --main not usable with SystemC. Suggest see examples for sc_main().
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%Error: Exiting due to
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23
test_regress/t/t_flag_main_sc_bad.pl
Executable file
23
test_regress/t/t_flag_main_sc_bad.pl
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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compile(
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verilator_flags2 => ['--exe --build --main --sc'],
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verilator_make_cmake => 0,
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verilator_make_gmake => 0,
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make_main => 0,
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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1
test_regress/t/t_flag_nofile_bad.out
Normal file
1
test_regress/t/t_flag_nofile_bad.out
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@ -0,0 +1 @@
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%Error: verilator: No Input Verilog file specified on command line, see verilator --help for more information
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21
test_regress/t/t_flag_nofile_bad.pl
Executable file
21
test_regress/t/t_flag_nofile_bad.pl
Executable file
@ -0,0 +1,21 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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run(cmd => ["../bin/verilator --lint-only"],
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fails => 1,
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logfile => "$Self->{obj_dir}/sim.log",
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expect_filename => $Self->{golden_filename},
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verilator_run => 1,
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);
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ok(1);
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1;
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@ -48,7 +48,7 @@ compile( # Don't call cmake nor gmake from driver.pl. Just build here
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verilator_make_gmake => 0,
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verilator_flags2 => ['--exe --cc --build --no-verilate',
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'../' . $Self->{main_filename},
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'--debugi 1 --dump-tree'],
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'--debugi 1 --dump-tree --dump-tree-addrids'],
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);
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# The previous run must not verilated, only build is expected.
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1
test_regress/t/t_flag_werror_bad3.out
Normal file
1
test_regress/t/t_flag_werror_bad3.out
Normal file
@ -0,0 +1 @@
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%Error: Unknown warning specified: -Werror-NOSUCHERRORASTHIS
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test_regress/t/t_flag_werror_bad3.pl
Executable file
22
test_regress/t/t_flag_werror_bad3.pl
Executable file
@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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top_filename("t/t_flag_werror.v");
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lint(
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fails => 1,
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verilator_flags => [qw(-cc -Werror-NOSUCHERRORASTHIS)],
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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1
test_regress/t/t_flag_woff_bad.out
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1
test_regress/t/t_flag_woff_bad.out
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@ -0,0 +1 @@
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%Error: Unknown warning specified: -Wno-NOSUCHERRORASTHIS
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test_regress/t/t_flag_woff_bad.pl
Executable file
20
test_regress/t/t_flag_woff_bad.pl
Executable file
@ -0,0 +1,20 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2008 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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lint(
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verilator_flags2 => ["--lint-only -Wno-NOSUCHERRORASTHIS"],
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fails => 1,
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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1
test_regress/t/t_flag_wwarn_bad.out
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1
test_regress/t/t_flag_wwarn_bad.out
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@ -0,0 +1 @@
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%Error: Unknown warning specified: -Wwarn-NOSUCHERRORASTHIS
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test_regress/t/t_flag_wwarn_bad.pl
Executable file
22
test_regress/t/t_flag_wwarn_bad.pl
Executable file
@ -0,0 +1,22 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(vlt => 1);
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top_filename("t/t_flag_werror.v");
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lint(
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fails => 1,
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verilator_flags => [qw(-cc -Wwarn-NOSUCHERRORASTHIS)],
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expect_filename => $Self->{golden_filename},
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);
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ok(1);
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1;
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@ -1,10 +1,19 @@
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%Error: t/t_func_return_bad.v:10:7: Return isn't underneath a task or function
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10 | return;
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%Error: t/t_func_return_bad.v:10:7: Return underneath a task shouldn't have return value
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10 | return 1;
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| ^~~~~~
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%Error: t/t_func_return_bad.v:11:7: continue isn't underneath a loop
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11 | continue;
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%Error: t/t_func_return_bad.v:13:7: Return underneath a function should have return value
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13 | return;
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| ^~~~~~
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%Error: t/t_func_return_bad.v:17:7: Return isn't underneath a task or function
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17 | return;
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| ^~~~~~
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%Error: t/t_func_return_bad.v:18:7: continue isn't underneath a loop
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18 | continue;
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| ^~~~~~~~
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%Error: t/t_func_return_bad.v:12:7: break isn't underneath a loop
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12 | break;
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%Error: t/t_func_return_bad.v:19:7: break isn't underneath a loop
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19 | break;
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| ^~~~~
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%Error: t/t_func_return_bad.v:22:7: disable isn't underneath a begin with name: 'foo'
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22 | disable foo;
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| ^~~~~~~
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%Error: Exiting due to
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@ -6,9 +6,19 @@
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module t (/*AUTOARG*/);
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task t1;
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return 1; // Shouldn't return value
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endtask
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function int f1;
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return; // Should return value
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endfunction
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initial begin
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return; // Not under function
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continue; // Not under loop
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break; // Not under loop
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begin : foo
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end
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disable foo; // Disabling outside block
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end
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endmodule
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0
test_regress/t/t_increment_bad.pl
Normal file → Executable file
0
test_regress/t/t_increment_bad.pl
Normal file → Executable file
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