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Fix false WIDTHCONCAT on casted constant (#2849).

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Wilson Snyder 2021-03-23 19:49:57 -04:00
parent 2e158d88c1
commit 7ea014dab5
3 changed files with 9 additions and 0 deletions
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@ -24,6 +24,7 @@ Verilator 4.201 devel
* Fix --timescale-override not suppressing TIMESCALEMOD (#2838). [Kaleb Barrett]
* Fix false TIMESCALEMOD on generate-ignored instances (#2838). [Kaleb Barrett]
* Fix --output-split with class extends (#2839). [Iru Cai]
* Fix false WIDTHCONCAT on casted constant (#2849). [Rupert Swarbrick]
Verilator 4.200 2021-03-12

1
src/V3Width.cpp
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@ -1821,6 +1821,7 @@ private:
if (m_vup->final()) {
// CastSize not needed once sizes determined
AstNode* underp = nodep->lhsp()->unlinkFrBack();
underp->dtypeFrom(nodep);
nodep->replaceWith(underp);
VL_DO_DANGLING(pushDeletep(nodep), nodep);
}

7
test_regress/t/t_cast.v
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@ -46,6 +46,10 @@ module t;
(27'(coeff1 * samp1) >>> 11) +
(27'(coeff2 * samp2) >>> 11)); // 15' size casting to avoid synthesis/simulator warnings
logic one = 1'b1;
logic [32:0] b33 = {32'(0), one};
logic [31:0] b32 = {31'(0), one};
initial begin
if (logic8bit != 8'h12) $stop;
if (4'shf > 4'sh0) $stop;
@ -79,6 +83,9 @@ module t;
if (27'h7ffecec != mida) $stop;
if (27'h7ffecec != midb) $stop;
if (b33 != 33'b1) $stop;
if (b32 != 32'b1) $stop;
$write("*-* All Finished *-*\n");
$finish;
end