From 7ca1d35a4eed0131ee9897e8232371529067013a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Fri, 16 Sep 2016 18:15:32 -0400
Subject: [PATCH] New test.

---
 test_regress/t/t_math_shift_over_bad.pl | 21 +++++++++++++++++++++
 test_regress/t/t_math_shift_over_bad.v  | 20 ++++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100755 test_regress/t/t_math_shift_over_bad.pl
 create mode 100644 test_regress/t/t_math_shift_over_bad.v

diff --git a/test_regress/t/t_math_shift_over_bad.pl b/test_regress/t/t_math_shift_over_bad.pl
new file mode 100755
index 000000000..e579e55f5
--- /dev/null
+++ b/test_regress/t/t_math_shift_over_bad.pl
@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2010 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    verilator_flags2 => ["--lint-only"],
+    fails=>1,
+    expect=>
+'%Error: Internal Error: .*: Value too wide for 32-bits expected in this context 64\'h123456789abcdef
+.',
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_math_shift_over_bad.v b/test_regress/t/t_math_shift_over_bad.v
new file mode 100644
index 000000000..c7005817c
--- /dev/null
+++ b/test_regress/t/t_math_shift_over_bad.v
@@ -0,0 +1,20 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2016 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Outputs
+   o,
+   // Inputs
+   clk, i
+   );
+
+   input clk;
+
+   input [31:0] i;
+   output [31:0] o;
+
+   assign o = i << 64'h01234567_89abcdef;
+
+endmodule