forked from github/verilator
Error reproduced
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@ -24,6 +24,11 @@ module t;
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// bug925
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// bug925
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localparam [6:0] RESULT = 7'((6*9+92)%96);
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localparam [6:0] RESULT = 7'((6*9+92)%96);
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// bug2070
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logic [511:0] array;
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logic [63:0] slice;
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localparam ARRAY_SLICE = 64;
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assign slice = array[(3'(3) - 3'(1)) * ARRAY_SLICE +: ARRAY_SLICE];
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logic signed [14:0] samp0 = 15'h0000;
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logic signed [14:0] samp0 = 15'h0000;
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logic signed [14:0] samp1 = 15'h0000;
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logic signed [14:0] samp1 = 15'h0000;
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