forked from github/verilator
Internals: Pass unconnected pins through structures. No functional change intended.
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@ -114,6 +114,7 @@ private:
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// we'll save work, and we can't call pinReconnectSimple in
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// this loop as it clone()s itself.
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for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
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if (!pinp->exprp()) continue;
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V3Inst::pinReconnectSimple(pinp, nodep, m_modp);
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}
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@ -130,6 +131,7 @@ private:
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m_modp->addInlinesp(inlinep); // Must be parsed before any AstCells
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// Create assignments to the pins
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for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
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if (!pinp->exprp()) continue;
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UINFO(6," Pin change from "<<pinp->modVarp()<<endl);
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// Make new signal; even though we'll optimize the interconnect, we
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// need an alias to trace correctly. If tracing is disabled, we'll
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@ -80,6 +80,7 @@ private:
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// PIN(p,expr) -> ASSIGNW(VARXREF(p),expr) (if sub's input)
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// or ASSIGNW(expr,VARXREF(p)) (if sub's output)
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UINFO(4," PIN "<<nodep<<endl);
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if (!nodep->exprp()) return; // No-connect
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if (debug()>=9) nodep->dumpTree(cout," Pin_oldb: ");
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if (nodep->modVarp()->isOutOnly() && nodep->exprp()->castConst())
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nodep->v3error("Output port is connected to a constant pin, electrical short");
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@ -188,6 +189,7 @@ private:
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}
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virtual void visit(AstPin* nodep, AstNUser*) {
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// Any non-direct pins need reconnection with a part-select
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if (!nodep->exprp()) return; // No-connect
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if (m_cellRangep) {
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UINFO(4," PIN "<<nodep<<endl);
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int pinwidth = nodep->modVarp()->width();
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@ -656,13 +656,6 @@ private:
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refp->user5p(nodep);
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}
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}
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if (!nodep->exprp()) {
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// It's an empty pin connection, done with it.
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// (We used to not create pins for these, but we'd miss
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// warns. Perhaps they should live even further...)
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pushDeletep(nodep->unlinkFrBack()); nodep=NULL;
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return;
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}
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nodep->iterateChildren(*this);
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}
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// Deal with implicit definitions - do before ID_RESOLVE stage as may be referenced above declaration
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@ -311,6 +311,7 @@ void ParamVisitor::visit(AstCell* nodep, AstNUser*) {
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if (debug()>8) nodep->paramsp()->dumpTreeAndNext(cout,"-cellparams:\t");
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for (AstPin* pinp = nodep->paramsp(); pinp; pinp=pinp->nextp()->castPin()) {
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if (!pinp) nodep->v3fatalSrc("Non pin under cell params\n");
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if (!pinp->exprp()) continue; // No-connect
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AstVar* modvarp = pinp->modVarp();
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if (!modvarp) {
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pinp->v3error("Parameter not found in sub-module: Param "<<pinp->name()<<" of "<<nodep->prettyName());
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@ -390,7 +391,7 @@ void ParamVisitor::visit(AstCell* nodep, AstNUser*) {
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// Assign parameters to the constants specified
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for (AstPin* pinp = nodep->paramsp(); pinp; pinp=pinp->nextp()->castPin()) {
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AstVar* modvarp = pinp->modVarp();
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if (modvarp) {
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if (modvarp && pinp->exprp()) {
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AstConst* constp = pinp->exprp()->castConst();
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// Remove any existing parameter
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if (modvarp->valuep()) modvarp->valuep()->unlinkFrBack()->deleteTree();
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@ -475,6 +475,7 @@ class TristateVisitor : public TristateBaseVisitor {
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// ENABLE: -> (VARREF(trisig__pinen)
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// SEL(trisig,x) = BUFIF1(enable__temp, trisig__pinen)
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UINFO(9," "<<nodep<<endl);
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if (!nodep->exprp()) return; // No-connect
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AstVar* enModVarp = (AstVar*) nodep->modVarp()->user1p();
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if (!enModVarp) { // no __en signals on this pin
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nodep->iterateChildren(*this);
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@ -1097,11 +1097,15 @@ private:
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if (nodep->modVarp() && nodep->modVarp()->isGParam()) {
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// Widthing handled as special init() case
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nodep->iterateChildren(*this,WidthVP(ANYSIZE,0,BOTH).p());
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} else if (!m_paramsOnly){
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} else if (!m_paramsOnly) {
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if (nodep->modVarp()->width()==0) {
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// Var hasn't been widthed, so make it so.
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nodep->modVarp()->iterate(*this);
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}
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if (!nodep->exprp()) { // No-connect
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nodep->widthSignedFrom(nodep->modVarp());
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return;
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}
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// Very much like like an assignment, but which side is LH/RHS
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// depends on pin being a in/output/inout.
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nodep->exprp()->iterateAndNext(*this,WidthVP(ANYSIZE,0,PRELIM).p());
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