diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index 1fcc89a7c..f8edd6d32 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -4273,6 +4273,17 @@ public:
     virtual bool same(const AstNode* samep) const { return true; }
 };
 
+class AstWait : public AstNodeStmt {
+public:
+    AstWait(FileLine* fl, AstNode* condp, AstNode* bodysp)
+        : ASTGEN_SUPER(fl) {
+        setOp2p(condp);
+        addNOp3p(bodysp);
+    }
+    ASTNODE_NODE_FUNCS(Wait)
+    AstNode* bodysp() const { return op3p(); }  // op3 = body of loop
+};
+
 class AstWhile : public AstNodeStmt {
 public:
     AstWhile(FileLine* fl, AstNode* condp, AstNode* bodysp, AstNode* incsp = NULL)
diff --git a/src/V3LinkDot.cpp b/src/V3LinkDot.cpp
index 89db5174e..e5a057ef3 100644
--- a/src/V3LinkDot.cpp
+++ b/src/V3LinkDot.cpp
@@ -2036,8 +2036,7 @@ private:
         if (nodep->name() == "this") {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: this");
             m_ds.m_dotErr = true;
-        }
-        else if (nodep->name() == "super") {
+        } else if (nodep->name() == "super") {
             nodep->v3warn(E_UNSUPPORTED, "Unsupported: super");
             m_ds.m_dotErr = true;
         }
diff --git a/src/V3LinkJump.cpp b/src/V3LinkJump.cpp
index d31b5ba4d..56ff84b93 100644
--- a/src/V3LinkJump.cpp
+++ b/src/V3LinkJump.cpp
@@ -173,6 +173,17 @@ private:
         nodep->replaceWith(newp);
         VL_DO_DANGLING(nodep->deleteTree(), nodep);
     }
+    virtual void visit(AstWait* nodep) VL_OVERRIDE {
+        nodep->v3warn(E_UNSUPPORTED, "Unsupported: wait statements");
+        // Statements we'll just execute immediately; equivalent to if they followed this
+        if (AstNode* bodysp = nodep->bodysp()) {
+            bodysp->unlinkFrBackWithNext();
+            nodep->replaceWith(bodysp);
+        } else {
+            nodep->unlinkFrBack();
+        }
+        VL_DO_DANGLING(nodep->deleteTree(), nodep);
+    }
     virtual void visit(AstWhile* nodep) VL_OVERRIDE {
         // Don't need to track AstRepeat/AstFor as they have already been converted
         AstWhile* lastLoopp = m_loopp;
diff --git a/src/verilog.y b/src/verilog.y
index 793911f67..ad2566570 100644
--- a/src/verilog.y
+++ b/src/verilog.y
@@ -3079,7 +3079,7 @@ statement_item<nodep>:		// IEEE: statement_item
 	|	seq_block				{ $$ = $1; }
 	//
 	//			// IEEE: wait_statement
-	|	yWAIT '(' expr ')' stmtBlock		{ $$ = NULL; BBUNSUP($1, "Unsupported: wait statements"); }
+	|	yWAIT '(' expr ')' stmtBlock		{ $$ = new AstWait($1, $3, $5); }
 	|	yWAIT yFORK ';'				{ $$ = new AstWaitFork($1); }
 	//UNSUP	yWAIT_ORDER '(' hierarchical_identifierList ')' action_block	{ UNSUP }
 	//
diff --git a/test_regress/t/t_wait.out b/test_regress/t/t_wait.out
new file mode 100644
index 000000000..bc88a4f78
--- /dev/null
+++ b/test_regress/t/t_wait.out
@@ -0,0 +1,13 @@
+%Error-UNSUPPORTED: t/t_wait.v:12:7: Unsupported: wait statements
+   12 |       wait (value == 1);
+      |       ^~~~
+%Error-UNSUPPORTED: t/t_wait.v:14:7: Unsupported: wait statements
+   14 |       wait (0);
+      |       ^~~~
+%Error-UNSUPPORTED: t/t_wait.v:17:7: Unsupported: wait statements
+   17 |       wait (value == 2);
+      |       ^~~~
+%Error-UNSUPPORTED: t/t_wait.v:20:7: Unsupported: wait statements
+   20 |       wait (value == 3) if (value != 3) $stop;
+      |       ^~~~
+%Error: Exiting due to
diff --git a/test_regress/t/t_wait.pl b/test_regress/t/t_wait.pl
new file mode 100755
index 000000000..89ffd046b
--- /dev/null
+++ b/test_regress/t/t_wait.pl
@@ -0,0 +1,20 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(linter => 1);
+
+lint(
+    verilator_flags2 => ['--lint-only'],
+    fails => 1,
+    expect_filename => $Self->{golden_filename},
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_wait.v b/test_regress/t/t_wait.v
new file mode 100644
index 000000000..ce59deadc
--- /dev/null
+++ b/test_regress/t/t_wait.v
@@ -0,0 +1,38 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t(/*AUTOARG*/);
+
+   int value;
+
+   initial begin
+      wait (value == 1);
+      if (value != 1) $stop;
+      wait (0);
+      if (value != 1) $stop;
+      //
+      wait (value == 2);
+      if (value != 2) $stop;
+      //
+      wait (value == 3) if (value != 3) $stop;
+      if (value != 3) $stop;
+   end
+
+   initial begin
+      #10;
+      value = 1;
+      #10;
+      value = 2;
+      #10;
+      value = 3;
+      #10;
+      value = 4;
+      #10;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+
+endmodule