forked from github/verilator
verilator_gantt: Fix argument report omitting last digits
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parent
33650336f5
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741bb5328e
@ -36,8 +36,8 @@ def read_data(filename):
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re_eval = re.compile(r'^VLPROF eval\sstart\s(\d+)\selapsed\s(\d+)')
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re_loop = re.compile(
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r'^VLPROF eval_loop\sstart\s(\d+)\selapsed\s(\d+)')
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re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.])\s*')
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re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.])\s*$')
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re_arg1 = re.compile(r'VLPROF arg\s+(\S+)\+([0-9.]*)\s*')
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re_arg2 = re.compile(r'VLPROF arg\s+(\S+)\s+([0-9.]*)\s*$')
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re_stat = re.compile(r'VLPROF stat\s+(\S+)\s+([0-9.]+)')
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re_time = re.compile(r'rdtsc time = (\d+) ticks')
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re_proc_cpu = re.compile(r'VLPROFPROC processor\s*:\s*(\d+)\s*$')
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@ -81,7 +81,7 @@ private:
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virtual void visit(AstNode* nodep) override {
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#if VL_DEBUG
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UINFO(0, "%Warning: Hashing node as AstNode: " << nodep);
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UINFO(0, "%Warning: Hashing node as AstNode: " << nodep << endl);
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#endif
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m_hash += hashNodeAndIterate(nodep, HASH_DTYPE, HASH_CHILDREN, [=]() {});
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}
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@ -8,8 +8,6 @@ if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); di
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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use IO::File;
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# Test for bin/verilator_gantt,
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#
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# Only needed in multithreaded regression.
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