From 72b2df30f80cee24afe736edfdce7052429a0a6a Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Mon, 28 Dec 2020 11:13:58 -0500
Subject: [PATCH] Fix tracing empty sc module (#2729).

---
 Changes                            |  2 ++
 src/V3Trace.cpp                    |  3 ++-
 test_regress/t/t_trace_sc_empty.pl | 18 ++++++++++++++++++
 test_regress/t/t_trace_sc_empty.v  | 14 ++++++++++++++
 4 files changed, 36 insertions(+), 1 deletion(-)
 create mode 100755 test_regress/t/t_trace_sc_empty.pl
 create mode 100644 test_regress/t/t_trace_sc_empty.v

diff --git a/Changes b/Changes
index 83bfa4136..959025263 100644
--- a/Changes
+++ b/Changes
@@ -29,6 +29,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix vpi_release_handle to be called implicitly per IEEE (#2706).
 
+****  Fix tracing empty sc module (#2729).
+
 
 * Verilator 4.106 2020-12-02
 
diff --git a/src/V3Trace.cpp b/src/V3Trace.cpp
index 33b37a568..19f9191e8 100644
--- a/src/V3Trace.cpp
+++ b/src/V3Trace.cpp
@@ -604,7 +604,8 @@ private:
             AstCFunc* topFuncp = nullptr;
             AstCFunc* subFuncp = nullptr;
             int subStmts = 0;
-            const uint32_t maxCodes = (nAllCodes + parallelism - 1) / parallelism;
+            uint32_t maxCodes = (nAllCodes + parallelism - 1) / parallelism;
+            if (maxCodes < 1) maxCodes = 1;
             uint32_t nCodes = 0;
             const ActCodeSet* prevActSet = nullptr;
             AstIf* ifp = nullptr;
diff --git a/test_regress/t/t_trace_sc_empty.pl b/test_regress/t/t_trace_sc_empty.pl
new file mode 100755
index 000000000..e8d7ccc84
--- /dev/null
+++ b/test_regress/t/t_trace_sc_empty.pl
@@ -0,0 +1,18 @@
+#!/usr/bin/env perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2019 by Wilson Snyder. This program is free software; you
+# can redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
+
+scenarios(simulator => 1);
+
+compile(
+    verilator_flags2 => ['-sc', '--trace'],
+    );
+
+ok(1);
+1;
diff --git a/test_regress/t/t_trace_sc_empty.v b/test_regress/t/t_trace_sc_empty.v
new file mode 100644
index 000000000..4136b8663
--- /dev/null
+++ b/test_regress/t/t_trace_sc_empty.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2020 by Wilsn Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+module t
+  (
+   output id0
+   );
+
+   assign id0 = 0;
+
+endmodule