Fix false name conflict on cells in generate blocks, bug749.

Changes

@@ -15,6 +15,8 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ****  Fix seg-fault with variable of parameterized interface, bug692. [Jie Xu]
 
+****  Fix false name conflict on cells in generate blocks, bug749. [Igor Lesik]
+
 ****  Fix pattern assignment to basic types, bug767. [Jie Xu]
 
 ****  Fix pattern assignment to conditionals, bug769. [Jie Xu]

src/V3LinkDot.cpp

@@ -266,8 +266,8 @@ public:
 	if (nodep->modp()) nodep->modp()->user1p(symp);
 	checkDuplicate(abovep, nodep, nodep->origName());
 	abovep->reinsert(nodep->origName(), symp);
-	if (abovep != modSymp && !modSymp->findIdFlat(nodep->name())) {
-	    // If it's foo_DOT_bar, we need to be able to find it under that too.
+	if (forScopeCreation() && abovep != modSymp && !modSymp->findIdFlat(nodep->name())) {
+	    // If it's foo_DOT_bar, we need to be able to find it under "foo_DOT_bar" too.
 	    // Duplicates are possible, as until resolve generates might have 2 same cells under an if
 	    modSymp->reinsert(nodep->name(), symp);
 	}

test_regress/t/t_gen_for_overlap.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+compile (
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_gen_for_overlap.v

@@ -0,0 +1,49 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2014 by Wilson Snyder.
+
+// bug749
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   genvar g;
+   for (g=1; g<3; ++g) begin : gblk
+      sub2 #(.IN(g)) u ();
+      //sub #(.IN(g)) u2 ();
+   end
+
+   sub1 #(.IN(0)) u ();
+
+   always @ (posedge clk) begin
+      if (t.u.IN != 0) $stop;
+      if (t.u.FLAVOR != 1) $stop;
+      //if (t.u2.IN != 0) $stop;  // This should be not found
+      if (t.gblk[1].u.IN != 1) $stop;
+      if (t.gblk[2].u.IN != 2) $stop;
+      if (t.gblk[1].u.FLAVOR != 2) $stop;
+      if (t.gblk[2].u.FLAVOR != 2) $stop;
+      $write("*-* All Finished *-*\n");
+      $finish;
+   end
+endmodule
+
+module sub1 (/*AUTOARG*/);
+   parameter [31:0] IN = 99;
+   parameter FLAVOR = 1;
+`ifdef TEST_VERBOSE
+   initial $display("%m");
+`endif
+endmodule
+
+module sub2 (/*AUTOARG*/);
+   parameter [31:0] IN = 99;
+   parameter FLAVOR = 2;
+`ifdef TEST_VERBOSE
+   initial $display("%m");
+`endif
+endmodule