forked from github/verilator
Fix internal error on dotted refs into generates, bug958.
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
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* Verilator 3.877 devel
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**** Fix internal error on dotted refs into generates, bug958. [Jie Xu]
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**** Fix mis-optimizing public DPI functions, bug963. [Wei Song]
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@ -186,11 +186,15 @@ private:
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// NODE STATE
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// Nothing! // This may be called deep inside other routines
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// // so userp and friends may not be used
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// VISITORS
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virtual void visit(AstNode* nodep, AstNUser*) {
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// METHODS
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void processAndIterate(AstNode* nodep) {
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BrokenTable::addInTree(nodep, nodep->maybePointedTo());
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nodep->iterateChildrenConst(*this);
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}
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// VISITORS
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virtual void visit(AstNode* nodep, AstNUser*) {
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processAndIterate(nodep);
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}
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public:
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// CONSTUCTORS
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BrokenMarkVisitor(AstNetlist* nodep) {
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@ -210,7 +214,7 @@ private:
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nodep->v3fatalSrc("Width != WidthMin");
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}
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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void processAndIterate(AstNode* nodep) {
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BrokenTable::setUnder(nodep,true);
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if (const char* whyp=nodep->broken()) {
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nodep->v3fatalSrc("Broken link in node (or something without maybePointedTo): "<<whyp);
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@ -232,6 +236,9 @@ private:
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nodep->iterateChildrenConst(*this);
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BrokenTable::setUnder(nodep,false);
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}
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virtual void visit(AstNode* nodep, AstNUser*) {
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processAndIterate(nodep);
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}
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public:
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// CONSTUCTORS
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BrokenCheckVisitor(AstNetlist* nodep) {
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@ -248,6 +248,9 @@ private:
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virtual void visit(AstVarRef* nodep, AstNUser*) {
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if (nodep->varp()) nodep->varp()->iterate(*this);
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}
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virtual void visit(AstVarXRef* nodep, AstNUser*) {
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nodep->varp(NULL); // Needs relink, as may remove pointed-to var
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}
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// Generate Statements
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virtual void visit(AstGenerate* nodep, AstNUser*) {
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15
test_regress/t/t_var_xref_gen.pl
Executable file
15
test_regress/t/t_var_xref_gen.pl
Executable file
@ -0,0 +1,15 @@
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#!/usr/bin/perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2003 by Wilson Snyder. This program is free software; you can
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# redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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compile (
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verilator_flags2 => ["--debug-check"],
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);
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ok(1);
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1;
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43
test_regress/t/t_var_xref_gen.v
Normal file
43
test_regress/t/t_var_xref_gen.v
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@ -0,0 +1,43 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This is to test the handling of VarXRef when the referenced VAR is
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// under a generate construction.
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//
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// This file ONLY is placed into the Public Domain, for any use,
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// without warranty, 2015 by Jie Xu and Roland Kruse.
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module t (/*AUTOARG*/
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// Inputs
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clk, addr, res
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);
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input clk;
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input [31:0] addr;
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output [15:0] res;
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memory i_mem(.addr(addr),.dout(res));
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assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0;
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endmodule
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module memory(addr, dout);
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parameter CM_XROWSIZE = 256;
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parameter CM_NUMXROWS = 2;
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input [31:0] addr;
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output [15:0] dout;
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generate
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genvar g_cx;
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for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++)
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begin: cxrow_inst
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reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1];
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end
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endgenerate
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assign dout = cxrow_inst[0].cmem_xrow[addr];
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endmodule
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