Fix internal error on dotted refs into generates, bug958.

This commit is contained in:
Wilson Snyder 2015-09-18 20:57:27 -04:00
parent d0ec991bb2
commit 7163c8d048
5 changed files with 73 additions and 3 deletions

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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.877 devel
**** Fix internal error on dotted refs into generates, bug958. [Jie Xu]
**** Fix mis-optimizing public DPI functions, bug963. [Wei Song]

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@ -186,11 +186,15 @@ private:
// NODE STATE
// Nothing! // This may be called deep inside other routines
// // so userp and friends may not be used
// VISITORS
virtual void visit(AstNode* nodep, AstNUser*) {
// METHODS
void processAndIterate(AstNode* nodep) {
BrokenTable::addInTree(nodep, nodep->maybePointedTo());
nodep->iterateChildrenConst(*this);
}
// VISITORS
virtual void visit(AstNode* nodep, AstNUser*) {
processAndIterate(nodep);
}
public:
// CONSTUCTORS
BrokenMarkVisitor(AstNetlist* nodep) {
@ -210,7 +214,7 @@ private:
nodep->v3fatalSrc("Width != WidthMin");
}
}
virtual void visit(AstNode* nodep, AstNUser*) {
void processAndIterate(AstNode* nodep) {
BrokenTable::setUnder(nodep,true);
if (const char* whyp=nodep->broken()) {
nodep->v3fatalSrc("Broken link in node (or something without maybePointedTo): "<<whyp);
@ -232,6 +236,9 @@ private:
nodep->iterateChildrenConst(*this);
BrokenTable::setUnder(nodep,false);
}
virtual void visit(AstNode* nodep, AstNUser*) {
processAndIterate(nodep);
}
public:
// CONSTUCTORS
BrokenCheckVisitor(AstNetlist* nodep) {

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@ -248,6 +248,9 @@ private:
virtual void visit(AstVarRef* nodep, AstNUser*) {
if (nodep->varp()) nodep->varp()->iterate(*this);
}
virtual void visit(AstVarXRef* nodep, AstNUser*) {
nodep->varp(NULL); // Needs relink, as may remove pointed-to var
}
// Generate Statements
virtual void visit(AstGenerate* nodep, AstNUser*) {

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@ -0,0 +1,15 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# Lesser General Public License Version 3 or the Perl Artistic License
# Version 2.0.
compile (
verilator_flags2 => ["--debug-check"],
);
ok(1);
1;

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@ -0,0 +1,43 @@
// DESCRIPTION: Verilator: Verilog Test module
//
// This is to test the handling of VarXRef when the referenced VAR is
// under a generate construction.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Jie Xu and Roland Kruse.
module t (/*AUTOARG*/
// Inputs
clk, addr, res
);
input clk;
input [31:0] addr;
output [15:0] res;
memory i_mem(.addr(addr),.dout(res));
assign i_mem.cxrow_inst[0].cmem_xrow[0] = 16'h0;
endmodule
module memory(addr, dout);
parameter CM_XROWSIZE = 256;
parameter CM_NUMXROWS = 2;
input [31:0] addr;
output [15:0] dout;
generate
genvar g_cx;
for (g_cx = 0; g_cx < CM_NUMXROWS; g_cx++)
begin: cxrow_inst
reg [15:0] cmem_xrow[0:CM_XROWSIZE - 1];
end
endgenerate
assign dout = cxrow_inst[0].cmem_xrow[addr];
endmodule