forked from github/verilator
Fix per-bit array output connection error, bug414.
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@ -30,6 +30,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix segfault on multidimensional dotted arrays, bug607. [Jie Xu]
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**** Fix per-bit array output connection error, bug414. [Jan Egil Ruud]
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**** Fix package logic var compile error.
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**** Fix enums with X values.
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@ -198,6 +198,7 @@ private:
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AstNode* exprp = nodep->exprp()->unlinkFrBack();
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bool inputPin = nodep->modVarp()->isInput();
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if (!inputPin && !exprp->castVarRef()
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&& !exprp->castConcat() // V3Const will collapse the SEL with the one we're about to make
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&& !exprp->castSel()) { // V3Const will collapse the SEL with the one we're about to make
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nodep->v3error("Unsupported: Per-bit array instantiations with output connections to non-wires.");
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// Note spec allows more complicated matches such as slices and such
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@ -9,8 +9,8 @@ module t (/*AUTOARG*/
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);
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input clk;
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wire [17:10] bitout;
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wire [27:24] short_bitout;
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wire [19:10] bitout;
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wire [29:24] short_bitout;
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wire [7:0] allbits;
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wire [15:0] twobits;
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@ -37,6 +37,11 @@ module t (/*AUTOARG*/
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.twobits (twobits),
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.bitout (bitout[17:10]));
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sub
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i_sub6 [7:4] (.allbits (allbits),
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.twobits (twobits[15:8]),
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.bitout ({bitout[18+:2],short_bitout[28+:2]}));
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integer cyc=0;
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reg [63:0] crc;
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reg [63:0] sum;
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@ -44,7 +49,7 @@ module t (/*AUTOARG*/
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// Signals under test
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assign allbits = crc[7:0];
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assign twobits = crc[15:0];
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wire [63:0] result = {52'h0, short_bitout, bitout};
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wire [63:0] result = {48'h0, short_bitout, bitout};
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// Test loop
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always @ (posedge clk) begin
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@ -68,7 +73,7 @@ module t (/*AUTOARG*/
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$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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// What checksum will we end up with (above print should match)
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`define EXPECTED_SUM 64'h0bf9559ce1f98425
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`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
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if (sum !== `EXPECTED_SUM) $stop;
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$write("*-* All Finished *-*\n");
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$finish;
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