forked from github/verilator
Add clearer unsupported message for inside on array (#2566)
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@ -2134,6 +2134,9 @@ private:
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// Similar logic in V3Case
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inewp = irangep->newAndFromInside(nodep->exprp(), irangep->lhsp()->unlinkFrBack(),
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irangep->rhsp()->unlinkFrBack());
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} else if (auto* irangep = VN_CAST(itemp->dtypep(), UnpackArrayDType)) {
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irangep->v3error("Unsupported: inside on unpacked array");
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continue;
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} else {
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inewp = new AstEqWild(itemp->fileline(), nodep->exprp()->cloneTree(true),
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itemp->unlinkFrBack());
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4
test_regress/t/t_inside_unpack.out
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4
test_regress/t/t_inside_unpack.out
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@ -0,0 +1,4 @@
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%Error: t/t_inside_unpack.v:13:31: Unsupported: inside on unpacked array
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13 | localparam int CHECKLIST_P [2:0] = '{0, 1, 2};
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| ^
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%Error: Exiting due to
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23
test_regress/t/t_inside_unpack.pl
Executable file
23
test_regress/t/t_inside_unpack.pl
Executable file
@ -0,0 +1,23 @@
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#!/usr/bin/env perl
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if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
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# DESCRIPTION: Verilator: Verilog Test driver/expect definition
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#
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# Copyright 2019 by Wilson Snyder. This program is free software; you
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# can redistribute it and/or modify it under the terms of either the GNU
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# Lesser General Public License Version 3 or the Perl Artistic License
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# Version 2.0.
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# SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
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scenarios(simulator => 1);
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compile(
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fails => $Self->{vlt_all},
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expect_filename => $Self->{golden_filename},
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);
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execute(
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check_finished => 1,
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) if !$Self->{vlt_all};
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ok(1);
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1;
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54
test_regress/t/t_inside_unpack.v
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54
test_regress/t/t_inside_unpack.v
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@ -0,0 +1,54 @@
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// DESCRIPTION: Verilator: Verilog Test module
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//
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// This file ONLY is placed under the Creative Commons Public Domain, for
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// any use, without warranty, 2020 by Wilson Snyder.
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// SPDX-License-Identifier: CC0-1.0
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module t(/*AUTOARG*/
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// Inputs
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clk
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);
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input clk;
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localparam int CHECKLIST_P [2:0] = '{0, 1, 2};
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localparam HIT_LP = 1;
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localparam MISS_LP = 4;
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localparam HIT_INSIDE = HIT_LP inside {CHECKLIST_P};
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localparam MISS_INSIDE = MISS_LP inside {CHECKLIST_P};
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initial begin
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if (HIT_INSIDE != 1) $stop;
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if (MISS_INSIDE != 0) $stop;
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end
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integer cyc=0;
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int array [10];
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logic l;
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always @ (posedge clk) begin
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cyc <= cyc + 1;
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if (cyc == 0) begin
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// Setup
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array[0] = 10;
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array[1] = 20;
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array[9] = 90;
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end
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else if (cyc < 99) begin
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l = (10 inside {array});
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if (l != 1) $stop;
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l = (20 inside {array});
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if (l != 1) $stop;
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l = (90 inside {array});
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if (l != 1) $stop;
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l = (99 inside {array});
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if (l != 0) $stop;
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end
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else if (cyc == 99) begin
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$write("*-* All Finished *-*\n");
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$finish;
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end
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end
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endmodule
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