forked from github/verilator
Tests: Add coverage of missing include error.
This commit is contained in:
parent
aa65dfb1bc
commit
6903c52ef7
18
test_regress/t/t_preproc_inc_notfound_bad.out
Normal file
18
test_regress/t/t_preproc_inc_notfound_bad.out
Normal file
@ -0,0 +1,18 @@
|
||||
%Error: t/t_preproc_inc_notfound_bad.v:6: Cannot find include file: this_file_is_not_found.vh
|
||||
... Looked in:
|
||||
t/this_file_is_not_found.vh
|
||||
t/this_file_is_not_found.vh.v
|
||||
t/this_file_is_not_found.vh.sv
|
||||
obj_dir//this_file_is_not_found.vh
|
||||
obj_dir//this_file_is_not_found.vh.v
|
||||
obj_dir//this_file_is_not_found.vh.sv
|
||||
../include/this_file_is_not_found.vh
|
||||
../include/this_file_is_not_found.vh.v
|
||||
../include/this_file_is_not_found.vh.sv
|
||||
this_file_is_not_found.vh
|
||||
this_file_is_not_found.vh.v
|
||||
this_file_is_not_found.vh.sv
|
||||
obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh
|
||||
obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.v
|
||||
obj_vlt/t_preproc_inc_notfound_bad/this_file_is_not_found.vh.sv
|
||||
%Error: Exiting due to
|
18
test_regress/t/t_preproc_inc_notfound_bad.pl
Executable file
18
test_regress/t/t_preproc_inc_notfound_bad.pl
Executable file
@ -0,0 +1,18 @@
|
||||
#!/usr/bin/perl
|
||||
if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
|
||||
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
|
||||
#
|
||||
# Copyright 2003 by Wilson Snyder. This program is free software; you can
|
||||
# redistribute it and/or modify it under the terms of either the GNU
|
||||
# Lesser General Public License Version 3 or the Perl Artistic License
|
||||
# Version 2.0.
|
||||
|
||||
scenarios(linter => 1);
|
||||
|
||||
lint(
|
||||
fails => 1,
|
||||
expect_filename => $Self->{golden_filename},
|
||||
);
|
||||
|
||||
ok(1);
|
||||
1;
|
6
test_regress/t/t_preproc_inc_notfound_bad.v
Normal file
6
test_regress/t/t_preproc_inc_notfound_bad.v
Normal file
@ -0,0 +1,6 @@
|
||||
// DESCRIPTION: Verilator: Verilog Test module
|
||||
//
|
||||
// This file ONLY is placed into the Public Domain, for any use,
|
||||
// without warranty, 2019 by Wilson Snyder.
|
||||
|
||||
`include "this_file_is_not_found.vh"
|
Loading…
Reference in New Issue
Block a user