forked from github/verilator
Cleanup V3Gate, no functional change
This commit is contained in:
Geza Lore
parent
2ab6272cc7
commit
682a60e325
215
src/V3Gate.cpp
215
src/V3Gate.cpp
@ -558,141 +558,96 @@ public:
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void GateVisitor::optimizeSignals(bool allowMultiIn) {
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for (V3GraphVertex* itp = m_graph.verticesBeginp(); itp; itp = itp->verticesNextp()) {
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if (GateVarVertex* const vvertexp = dynamic_cast<GateVarVertex*>(itp)) {
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if (vvertexp->inEmpty()) {
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vvertexp->clearReducibleAndDedupable("inEmpty"); // Can't deal with no sources
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if (!vvertexp->isTop() // Ok if top inputs are driverless
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&& !vvertexp->varScp()->varp()->valuep()
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&& !vvertexp->varScp()->varp()->isSigPublic()) {
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UINFO(4, "No drivers " << vvertexp->varScp() << endl);
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if (false) {
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// If we warned here after constant propagation, what the user considered
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// reasonable logic may have disappeared. Issuing a warning would
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// thus be confusing. V3Undriven now handles this.
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vvertexp->varScp()->varp()->v3warn(
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UNDRIVEN, "Signal has no drivers: '"
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<< vvertexp->scopep()->prettyName() << "."
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<< vvertexp->varScp()->varp()->prettyName() << "'");
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}
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}
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} else if (!vvertexp->inSize1()) {
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// Can't deal with more than one src
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vvertexp->clearReducibleAndDedupable("size!1");
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GateVarVertex* const vvertexp = dynamic_cast<GateVarVertex*>(itp);
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// Consider "inlining" variables
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if (!vvertexp) continue;
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if (vvertexp->inEmpty()) { // Can't deal with no sources
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vvertexp->clearReducibleAndDedupable("inEmpty");
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} else if (!vvertexp->inSize1()) { // Can't deal with more than one src
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vvertexp->clearReducibleAndDedupable("size!1");
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}
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// Reduce it?
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if (!vvertexp->reducible()) continue;
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// Grab the driving logic
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GateLogicVertex* const logicVertexp
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= static_cast<GateLogicVertex*>(vvertexp->inBeginp()->fromp());
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if (!logicVertexp->reducible()) continue;
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// Can we eliminate?
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AstNode* const logicp = logicVertexp->nodep();
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const GateOkVisitor okVisitor{logicp, vvertexp->isClock(), false};
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// Was it ok?
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if (!okVisitor.isSimple()) continue;
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// Does it read multiple source variables?
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if (okVisitor.rhsVarRefs().size() > 1) {
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if (!allowMultiIn) continue;
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// Do it if not used, or used only once, ignoring traces
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int n = 0;
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for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep; edgep = edgep->outNextp()) {
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const GateLogicVertex* const consumeVertexp
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= static_cast<GateLogicVertex*>(edgep->top());
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// Ignore tracing or other slow path junk, or if the destination is not used
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if (!consumeVertexp->slow() && consumeVertexp->outBeginp()) n += edgep->weight();
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if (n > 1) break;
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}
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// Reduce it?
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if (!vvertexp->reducible()) {
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UINFO(8, "SigNotRed " << vvertexp->name() << endl);
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if (n > 1) continue;
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}
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// Process it
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AstNode* const substp = okVisitor.substTree();
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if (debug() >= 5) logicp->dumpTree(cout, " elimVar: ");
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if (debug() >= 5) substp->dumpTree(cout, " subst: ");
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++m_statSigs;
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bool removedAllUsages = true;
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for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;) {
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GateLogicVertex* const consumeVertexp = static_cast<GateLogicVertex*>(edgep->top());
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AstNode* const consumerp = consumeVertexp->nodep();
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if (!elimLogicOkOutputs(consumeVertexp, okVisitor /*ref*/)) {
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// Cannot optimize this replacement
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removedAllUsages = false;
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edgep = edgep->outNextp();
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} else {
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UINFO(8, "Sig " << vvertexp->name() << endl);
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GateLogicVertex* const logicVertexp
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= dynamic_cast<GateLogicVertex*>(vvertexp->inBeginp()->fromp());
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UINFO(8, " From " << logicVertexp->name() << endl);
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AstNode* logicp = logicVertexp->nodep();
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if (logicVertexp->reducible()) {
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// Can we eliminate?
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const GateOkVisitor okVisitor{logicp, vvertexp->isClock(), false};
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const bool multiInputs = okVisitor.rhsVarRefs().size() > 1;
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// Was it ok?
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bool doit = okVisitor.isSimple();
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if (doit && multiInputs) {
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if (!allowMultiIn) doit = false;
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// Doit if one input, or not used, or used only once, ignoring traces
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int n = 0;
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for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;
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edgep = edgep->outNextp()) {
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const GateLogicVertex* const consumeVertexp
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= dynamic_cast<GateLogicVertex*>(edgep->top());
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if (!consumeVertexp->slow()) { // Not tracing or other slow path junk
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if (edgep->top()->outBeginp()) { // Destination is itself used
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n += edgep->weight();
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}
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}
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if (n > 1) {
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doit = false;
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break;
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}
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}
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}
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// Process it
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if (!doit) {
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if (allowMultiIn && (debug() >= 9)) {
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UINFO(9, "Not ok simp" << okVisitor.isSimple() << " mi" << multiInputs
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<< " ob" << vvertexp->outBeginp() << " on"
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<< (vvertexp->outBeginp()
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? vvertexp->outBeginp()->outNextp()
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: nullptr)
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<< " " << vvertexp->name() << endl);
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for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;
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edgep = edgep->outNextp()) {
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const GateLogicVertex* const consumeVertexp
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= dynamic_cast<GateLogicVertex*>(edgep->top());
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UINFO(9, " edge " << edgep << " to: " << consumeVertexp->nodep()
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<< endl);
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}
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for (V3GraphEdge* edgep = vvertexp->inBeginp(); edgep;
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edgep = edgep->inNextp()) {
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const GateLogicVertex* const consumeVertexp
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= dynamic_cast<GateLogicVertex*>(edgep->fromp());
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UINFO(9, " edge " << edgep << " from: "
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<< consumeVertexp->nodep() << endl);
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}
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}
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} else {
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AstNode* const substp = okVisitor.substTree();
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if (debug() >= 5) logicp->dumpTree(cout, " elimVar: ");
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if (debug() >= 5) substp->dumpTree(cout, " subst: ");
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++m_statSigs;
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bool removedAllUsages = true;
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for (V3GraphEdge* edgep = vvertexp->outBeginp(); edgep;) {
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GateLogicVertex* const consumeVertexp
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= dynamic_cast<GateLogicVertex*>(edgep->top());
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AstNode* const consumerp = consumeVertexp->nodep();
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if (!elimLogicOkOutputs(consumeVertexp, okVisitor /*ref*/)) {
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// Cannot optimize this replacement
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removedAllUsages = false;
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edgep = edgep->outNextp();
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} else {
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optimizeElimVar(vvertexp->varScp(), substp, consumerp);
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// If the new replacement referred to a signal,
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// Correct the graph to point to this new generating variable
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const GateVarRefList& rhsVarRefs = okVisitor.rhsVarRefs();
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for (GateVarRefList::const_iterator it = rhsVarRefs.begin();
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it != rhsVarRefs.end(); ++it) {
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AstVarScope* const newvarscp = (*it)->varScopep();
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UINFO(9, " Point-to-new vertex " << newvarscp << endl);
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GateVarVertex* const varvertexp = makeVarVertex(newvarscp);
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new V3GraphEdge(&m_graph, varvertexp, consumeVertexp, 1);
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// Propagate clock attribute onto generating node
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varvertexp->propagateAttrClocksFrom(vvertexp);
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}
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// Remove the edge
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VL_DO_DANGLING(edgep->unlinkDelete(), edgep);
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++m_statRefs;
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edgep = vvertexp->outBeginp();
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}
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}
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if (removedAllUsages) {
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// Remove input links
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while (V3GraphEdge* const edgep = vvertexp->inBeginp()) {
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VL_DO_DANGLING(edgep->unlinkDelete(), edgep);
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}
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// Clone tree so we remember it for tracing, and keep the pointer
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// to the "ALWAYS" part of the tree as part of this statement
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// That way if a later signal optimization that
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// retained a pointer to the always can
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// optimize it further
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logicp->unlinkFrBack();
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vvertexp->varScp()->valuep(logicp);
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logicp = nullptr;
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// Mark the vertex so we don't mark it as being
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// unconsumed in the next step
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vvertexp->user(true);
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logicVertexp->user(true);
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}
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}
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optimizeElimVar(vvertexp->varScp(), substp, consumerp);
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// If the new replacement referred to a signal,
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// Correct the graph to point to this new generating variable
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const GateVarRefList& rhsVarRefs = okVisitor.rhsVarRefs();
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for (AstNodeVarRef* const refp : rhsVarRefs) {
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AstVarScope* const newvarscp = refp->varScopep();
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GateVarVertex* const varvertexp = makeVarVertex(newvarscp);
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new V3GraphEdge(&m_graph, varvertexp, consumeVertexp, 1);
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// Propagate clock attribute onto generating node
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varvertexp->propagateAttrClocksFrom(vvertexp);
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}
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// Remove the edge
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VL_DO_DANGLING(edgep->unlinkDelete(), edgep);
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++m_statRefs;
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edgep = vvertexp->outBeginp();
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}
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}
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if (removedAllUsages) {
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// Remove input links
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while (V3GraphEdge* const edgep = vvertexp->inBeginp()) {
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VL_DO_DANGLING(edgep->unlinkDelete(), edgep);
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}
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// Clone tree so we remember it for tracing, and keep the pointer
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// to the "ALWAYS" part of the tree as part of this statement
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// That way if a later signal optimization that
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// retained a pointer to the always can
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// optimize it further
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VL_DO_DANGLING(vvertexp->varScp()->valuep(logicp->unlinkFrBack()), logicp);
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// Mark the vertex so we don't mark it as being
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// unconsumed in the next step
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vvertexp->user(true);
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logicVertexp->user(true);
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}
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}
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}
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