From 68046244dd82e27473094322bafdd56ba6ff3d51 Mon Sep 17 00:00:00 2001
From: Wilson Snyder <wsnyder@wsnyder.org>
Date: Tue, 24 Apr 2012 07:45:02 -0400
Subject: [PATCH] Fix 'output tri0' 2001 declaration; Var characteristics must
 be attributes

---
 src/V3AstNodes.cpp            |  7 +++++++
 src/V3AstNodes.h              |  6 +++++-
 src/V3Tristate.cpp            |  6 ++----
 test_regress/t/t_tri_pull01.v | 24 ++++++++++++++++++++----
 4 files changed, 34 insertions(+), 9 deletions(-)

diff --git a/src/V3AstNodes.cpp b/src/V3AstNodes.cpp
index 67b86c371..8c49f4b83 100644
--- a/src/V3AstNodes.cpp
+++ b/src/V3AstNodes.cpp
@@ -75,6 +75,9 @@ bool AstVar::isScBv() const {
 }
 
 void AstVar::combineType(AstVarType type) {
+    // These flags get combined with the existing settings of the flags.
+    // We don't test varType for certain types, instead set flags since
+    // when we combine wires cross-hierarchy we need a union of all characteristics.
     if (type == AstVarType::SUPPLY0) type = AstVarType::WIRE;
     if (type == AstVarType::SUPPLY1) type = AstVarType::WIRE;
     m_varType=type; 	// For debugging prints only
@@ -86,6 +89,10 @@ void AstVar::combineType(AstVarType type) {
     if (type==AstVarType::INOUT || type==AstVarType::TRIWIRE
 	|| type==AstVarType::TRI0 || type==AstVarType::TRI1)
 	m_tristate = true;
+    if (type==AstVarType::TRI0)
+	m_isPulldown = true;
+    if (type==AstVarType::TRI1)
+	m_isPullup = true;
 }
 
 string AstVar::verilogKwd() const {
diff --git a/src/V3AstNodes.h b/src/V3AstNodes.h
index d00a31ceb..bf6feab27 100644
--- a/src/V3AstNodes.h
+++ b/src/V3AstNodes.h
@@ -639,6 +639,8 @@ private:
     bool	m_fileDescr:1;	// File descriptor
     bool	m_isConst:1;	// Table contains constant data
     bool	m_isStatic:1;	// Static variable
+    bool	m_isPulldown:1;	// Tri0
+    bool	m_isPullup:1;	// Tri1
     bool	m_trace:1;	// Trace this variable
 
     void	init() {
@@ -649,7 +651,7 @@ private:
 	m_sigPublic=false; m_sigModPublic=false; m_sigUserRdPublic=false; m_sigUserRWPublic=false;
 	m_funcLocal=false; m_funcReturn=false;
 	m_attrClockEn=false; m_attrScBv=false; m_attrIsolateAssign=false; m_attrSFormat=false;
-	m_fileDescr=false; m_isConst=false; m_isStatic=false;
+	m_fileDescr=false; m_isConst=false; m_isStatic=false; m_isPulldown=false; m_isPullup=false;
 	m_trace=false;
     }
 public:
@@ -787,6 +789,8 @@ public:
     bool	isStatic() const { return m_isStatic; }
     bool	isFuncLocal() const { return m_funcLocal; }
     bool	isFuncReturn() const { return m_funcReturn; }
+    bool	isPullup() const { return m_isPullup; }
+    bool	isPulldown() const { return m_isPulldown; }
     bool	attrClockEn() const { return m_attrClockEn; }
     bool	attrScBv() const { return m_attrScBv; }
     bool	attrFileDescr() const { return m_fileDescr; }
diff --git a/src/V3Tristate.cpp b/src/V3Tristate.cpp
index 7a6b49301..d964e0ad4 100644
--- a/src/V3Tristate.cpp
+++ b/src/V3Tristate.cpp
@@ -589,12 +589,10 @@ class TristateVisitor : public TristateBaseVisitor {
 	m_varvec.push_back(nodep);
 	nodep->iterateChildren(*this);
 	// If tri0/1 force a pullup
-	bool pulldown = nodep->varType()==AstVarType::TRI0;
-	bool pullup = nodep->varType()==AstVarType::TRI1;
-	if (pulldown || pullup) {
+	if (nodep->isPulldown() || nodep->isPullup()) {
 	    AstNode* newp = new AstPull(nodep->fileline(),
 					new AstVarRef(nodep->fileline(), nodep, true),
-					pullup);
+					nodep->isPullup());
 	    m_modp->addStmtp(newp);
 	    // We'll iterate on the new AstPull later
 	}
diff --git a/test_regress/t/t_tri_pull01.v b/test_regress/t/t_tri_pull01.v
index 24a8ae634..e38765f8d 100644
--- a/test_regress/t/t_tri_pull01.v
+++ b/test_regress/t/t_tri_pull01.v
@@ -27,10 +27,14 @@ module t (/*AUTOARG*/
    bufif1 (t1, crc[2], cyc[1:0]==2'b10);
 
    tri 	t2;
-   t_tri t_tri (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
+   t_tri2 t_tri2 (.t2, .d(crc[1]), .oe(cyc[1:0]==2'b00));
    bufif1 (t2, crc[2], cyc[1:0]==2'b10);
 
-   wire [63:0] 	result = {55'h0, t2, 3'h0, t1, 3'h0, t0};
+   tri 	t3;
+   t_tri3 t_tri3 (.t3, .d(crc[1]), .oe(cyc[1:0]==2'b00));
+   bufif1 (t3, crc[2], cyc[1:0]==2'b10);
+
+   wire [63:0] 	result = {51'h0, t3, 3'h0,t2, 3'h0,t1, 3'h0,t0};
 
    // Test loop
    always @ (posedge clk) begin
@@ -54,7 +58,7 @@ module t (/*AUTOARG*/
 	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
 	 if (crc !== 64'hc77bb9b3784ea091) $stop;
 	 // What checksum will we end up with (above print should match)
-`define EXPECTED_SUM 64'hfb06f31a3805822e
+`define EXPECTED_SUM 64'h04f91df71371e950
 	 if (sum !== `EXPECTED_SUM) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
@@ -63,7 +67,7 @@ module t (/*AUTOARG*/
 
 endmodule
 
-module t_tri (/*AUTOARG*/
+module t_tri2 (/*AUTOARG*/
    // Outputs
    t2,
    // Inputs
@@ -75,3 +79,15 @@ module t_tri (/*AUTOARG*/
    tri1   t2;
    bufif1 (t2, d, oe);
 endmodule
+
+module t_tri3 (/*AUTOARG*/
+   // Outputs
+   t3,
+   // Inputs
+   d, oe
+   );
+   output tri1 t3;
+   input  d;
+   input  oe;
+   bufif1 (t3, d, oe);
+endmodule