diff --git a/Changes b/Changes index 49c934b1c..1e63f4b07 100644 --- a/Changes +++ b/Changes @@ -27,7 +27,7 @@ The contributors that suggested a given feature are shown in []. Thanks! **** Fix multithreaded yield behavior when no work. [Patrick Stewart] **** Fix bad-syntax crashes, bug1548, bug1550-1553, bug1557-1560, bug1563, - bug1573-1577, bug1582-1585. [Eric Rippey] + bug1573-1577, bug1582-1585, bug1591. [Eric Rippey] **** Fix false CMPCONST/UNSIGNED warnings on "inside", bug1581. [Mitch Hayenga] diff --git a/src/V3Simulate.h b/src/V3Simulate.h index e77878ba4..86601475f 100644 --- a/src/V3Simulate.h +++ b/src/V3Simulate.h @@ -396,7 +396,7 @@ private: clearOptimizable(nodep, "Var write & read"); } vscp->user1( vscp->user1() | VU_RV); - bool isConst = nodep->varp()->isParam(); + bool isConst = nodep->varp()->isParam() && nodep->varp()->valuep(); AstConst* constp = isConst ? fetchConstNull(nodep->varp()->valuep()) : NULL; if (isConst && constp) { // Propagate PARAM constants for constant function analysis if (!m_checkOnly && optimizable()) { diff --git a/src/V3Width.cpp b/src/V3Width.cpp index cd7e5bbc0..94044c01a 100644 --- a/src/V3Width.cpp +++ b/src/V3Width.cpp @@ -952,6 +952,7 @@ private: AstAttrOf* oldAttr = m_attrp; m_attrp = nodep; userIterateAndNext(nodep->fromp(), WidthVP(SELF, BOTH).p()); + if (nodep->dimp()) userIterateAndNext(nodep->dimp(), WidthVP(SELF, BOTH).p()); // Don't iterate children, don't want to lose VarRef. switch (nodep->attrType()) { case AstAttrType::VAR_BASE: @@ -981,9 +982,13 @@ private: "Unsized expression"); std::pair dim = nodep->fromp()->dtypep()->skipRefp()->dimensions(true); - uint32_t msbdim = dim.first+dim.second; - if (!nodep->dimp() || VN_IS(nodep->dimp(), Const) || msbdim<1) { - int dim = !nodep->dimp() ? 1 : VN_CAST(nodep->dimp(), Const)->toSInt(); + uint32_t msbdim = dim.first + dim.second; + if (!nodep->dimp() || msbdim < 1) { + int dim = 1; + AstConst* newp = dimensionValue(nodep->fromp()->dtypep(), nodep->attrType(), dim); + nodep->replaceWith(newp); nodep->deleteTree(); VL_DANGLING(nodep); + } else if (VN_IS(nodep->dimp(), Const)) { + int dim = VN_CAST(nodep->dimp(), Const)->toSInt(); AstConst* newp = dimensionValue(nodep->fromp()->dtypep(), nodep->attrType(), dim); nodep->replaceWith(newp); nodep->deleteTree(); VL_DANGLING(nodep); } diff --git a/test_regress/t/t_param_noval_bad.out b/test_regress/t/t_param_noval_bad.out new file mode 100644 index 000000000..054055470 --- /dev/null +++ b/test_regress/t/t_param_noval_bad.out @@ -0,0 +1,29 @@ +%Error: t/t_param_noval_bad.v:6: Parameter without initial value is never given value (IEEE 1800-2017 6.20.1): 'P' + : ... In instance t +module t #(parameter P); + ^ +%Warning-WIDTH: t/t_param_noval_bad.v:9: Logical Operator GENFOR expects 1 bit on the For Test Condition, but For Test Condition's VARREF 'P' generates 32 bits. + : ... In instance t + for (j=0; P; j++) + ^~~ + ... Use "/* verilator lint_off WIDTH */" and lint_on around source to disable this message. +%Error: t/t_param_noval_bad.v:9: Non-genvar used in generate for: 'j' + : ... In instance t + for (j=0; P; j++) + ^~~ +%Error: t/t_param_noval_bad.v:9: Loop unrolling failed. + : ... In instance t + for (j=0; P; j++) + ^~~ +%Error: t/t_param_noval_bad.v:9: Unsupported: Can't unroll generate for; Unable to unroll loop + : ... In instance t + for (j=0; P; j++) + ^~~ +%Error: t/t_param_noval_bad.v:9: For loop doesn't have genvar index, or is malformed + : ... In instance t + for (j=0; P; j++) + ^~~ +%Error: Internal Error: t/t_param_noval_bad.v:9: ../V3Param.cpp:505: GENFOR should have been wrapped in BEGIN + : ... In instance t + for (j=0; P; j++) + ^~~ diff --git a/test_regress/t/t_param_noval_bad.pl b/test_regress/t/t_param_noval_bad.pl new file mode 100755 index 000000000..573f98f12 --- /dev/null +++ b/test_regress/t/t_param_noval_bad.pl @@ -0,0 +1,18 @@ +#!/usr/bin/perl +if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; } +# DESCRIPTION: Verilator: Verilog Test driver/expect definition +# +# Copyright 2008 by Wilson Snyder. This program is free software; you can +# redistribute it and/or modify it under the terms of either the GNU +# Lesser General Public License Version 3 or the Perl Artistic License +# Version 2.0. + +scenarios(linter => 1); + +lint( + fails => 1, + expect_filename => $Self->{golden_filename}, + ); + +ok(1); +1; diff --git a/test_regress/t/t_param_noval_bad.v b/test_regress/t/t_param_noval_bad.v new file mode 100644 index 000000000..9575ca824 --- /dev/null +++ b/test_regress/t/t_param_noval_bad.v @@ -0,0 +1,12 @@ +// DESCRIPTION: Verilator: Verilog Test module +// +// This file ONLY is placed into the Public Domain, for any use, +// without warranty, 2019 by Wilson Snyder. + +module t #(parameter P); + generate + var j; + for (j=0; P; j++) + initial begin end + endgenerate +endmodule