Fix wrong dot resolution under inlining.

Changes

@@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
       Disabled unless -OD or -O3 used, please try it as may get some
       significant speedups.
 
+***   Fix wrong dot resolution under inlining. [Art Stamness]
+
 ****  Support pattern assignment features, bug616, bug617, bug618. [Ed Lander]
 
 ****  Support bind in $unit, bug602. [Ed Lander]

src/V3LinkDot.cpp

@@ -1114,10 +1114,14 @@ private:
     }
     virtual void visit(AstScope* nodep, AstNUser*) {
 	UINFO(8,"   "<<nodep<<endl);
+	VSymEnt* oldModSymp = m_modSymp;
+	VSymEnt* oldCurSymp = m_curSymp;
 	checkNoDot(nodep);
-	m_ds.m_dotSymp = m_curSymp = m_statep->getScopeSym(nodep);
+	m_ds.m_dotSymp = m_curSymp = m_modSymp = m_statep->getScopeSym(nodep);
 	nodep->iterateChildren(*this);
-	m_ds.m_dotSymp = m_curSymp = NULL;
+	m_ds.m_dotSymp = m_curSymp = m_modSymp = NULL;
+	m_modSymp = oldModSymp;
+	m_curSymp = oldCurSymp;
     }
     virtual void visit(AstCellInline* nodep, AstNUser*) {
 	checkNoDot(nodep);
@@ -1320,6 +1324,7 @@ private:
 			newp = new AstVarRef(nodep->fileline(), nodep->name(), false);  // lvalue'ness computed later
 			newp->varp(varp);
 			newp->packagep(foundp->packagep());
+			UINFO(9,"    new "<<newp<<endl);
 		    }
 		    nodep->replaceWith(newp); pushDeletep(nodep); nodep = NULL;
 		    m_ds.m_dotPos = DP_MEMBER;
@@ -1442,6 +1447,7 @@ private:
 		    AstVarRef* newvscp = new AstVarRef(nodep->fileline(), vscp, nodep->lvalue());
 		    nodep->replaceWith(newvscp);
 		    nodep->deleteTree(); nodep=NULL;
+		    UINFO(9,"         new "<<newvscp<<endl);  // Also prints taskp
 		}
 	    }
 	}

test_regress/t/t_inst_dtree.v

@@ -0,0 +1,71 @@
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2013 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+   
+`ifdef INLINE_A //verilator inline_module
+`else  //verilator no_inline_module
+`endif
+
+   bmod bsub3 (.clk, .n(3));
+   bmod bsub2 (.clk, .n(2));
+   bmod bsub1 (.clk, .n(1));
+   bmod bsub0 (.clk, .n(0));
+endmodule
+
+module bmod
+  (input  clk,
+   input [31:0] n);
+
+`ifdef INLINE_B //verilator inline_module
+`else  //verilator no_inline_module
+`endif
+
+   cmod csub (.clk, .n);
+
+endmodule
+
+module cmod
+  (input   clk, input [31:0] n);
+
+`ifdef INLINE_C //verilator inline_module
+`else  //verilator no_inline_module
+`endif
+
+   reg [31:0] clocal;
+   always @ (posedge clk) clocal <= n;
+
+   dmod dsub (.clk, .n);
+endmodule
+
+module dmod (input clk, input [31:0] n);
+
+`ifdef INLINE_D //verilator inline_module
+`else  //verilator no_inline_module
+`endif
+
+   reg [31:0] dlocal;
+   always @ (posedge clk) dlocal <= n;
+
+   int 	 cyc;
+   always @(posedge clk) begin
+      cyc <= cyc+1;
+   end
+   always @(posedge clk) begin
+      if (cyc>10) begin
+`ifdef TEST_VERBOSE $display("%m: csub.clocal=%0d  dlocal=%0d", csub.clocal, dlocal); `endif
+	 if (csub.clocal !== n) $stop;
+	 if (dlocal !== n) $stop;
+      end
+      if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+endmodule

test_regress/t/t_inst_dtree_inla.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_A'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlab.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_A +define+INLINE_B'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlac.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_A +define+INLINE_C'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlad.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_A +define+INLINE_D'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlb.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_B'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlbc.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_B +define+INLINE_C'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlbd.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_B +define+INLINE_D'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlc.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_C'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inlcd.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_C +define+INLINE_D'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_inst_dtree_inld.pl

@@ -0,0 +1,22 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+top_filename("t/t_inst_dtree.v");
+
+compile (
+    v_flags2 => ['+define+INLINE_D'],
+    verilator_flags2 => ['-trace'],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;