Fix compile error on public real parameters by suppressing, bug1261.

Changes

@@ -6,6 +6,8 @@ The contributors that suggested a given feature are shown in []. Thanks!
 
 ****  Fix compile error on public real parameters by suppressing, bug1261. [Alex Solomatnikov]
 
+****  Fix input-only tristate comparisons, bug1267. [Alexis G]
+
 ****  Remove c++filt, bug1265. [Stefan Wallentowitz]
 
 

src/V3Tristate.cpp

@@ -1117,10 +1117,12 @@ class TristateVisitor : public TristateBaseVisitor {
 	    }
 	    // Create new output pin
 	    AstAssignW* outAssignp = NULL;  // If reconnected, the related assignment
-	    AstPin* outpinp;
-	    {
-		AstVar* outModVarp = (AstVar*) nodep->modVarp()->user4p();
-		if (!outModVarp) nodep->v3fatalSrc("Unlinked");
+            AstPin* outpinp = NULL;
+            AstVar* outModVarp = (AstVar*) nodep->modVarp()->user4p();
+            if (!outModVarp) {
+                // At top, no need for __out as might be input only. Otherwise resolvable.
+                if (!m_modp->isTop()) nodep->v3fatalSrc("Unlinked");
+            } else {
 		AstNode* outexprp = nodep->exprp()->cloneTree(false);  // Note has lvalue() set
 		outpinp = new AstPin(nodep->fileline(),
 				     nodep->pinNum(),
@@ -1153,14 +1155,19 @@ class TristateVisitor : public TristateBaseVisitor {
 	    // Connect enable to output signal
 	    AstVarRef* exprrefp;  // Tristate variable that the Pin's expression refers to
 	    if (!outAssignp) {
-		exprrefp = outpinp->exprp()->castVarRef();
+                if (!outpinp) {
+                    exprrefp = NULL;  // Primary input only
+                } else {
+                    // pinReconnect should have converted this
+                    exprrefp = outpinp->exprp()->castVarRef();
+                    if (!exprrefp) nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
+                }
 	    } else {
+                // pinReconnect should have converted this
 		exprrefp = outAssignp->rhsp()->castVarRef();  // This should be the same var as the output pin
+                if (!exprrefp) nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
 	    }
-	    if (!exprrefp) { // deal with simple varref port
-		// pinReconnect should have converted this
-		nodep->v3error("Unsupported tristate port expression: "<<nodep->exprp()->prettyTypeName());
-	    } else {
+            if (exprrefp) {
 		UINFO(9,"outref "<<exprrefp<<endl);
 		exprrefp->user1p(enrefp);  // Mark as now tristated; iteration will pick it up from there
 		if (!outAssignp) {

test_regress/t/t_altera_lpm_abs.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_add_sub.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_and.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_bustri.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_clshift.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_compare.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_constant.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_counter.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_decode.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_divide.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ff.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_fifo.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_fifo_dc.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_inv.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_latch.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_mult.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_mux.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_or.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_dp.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_dq.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_ram_io.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_rom.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_shiftreg.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_altera_lpm_xor.pl

@@ -0,0 +1,20 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+top_filename("t/t_altera_lpm.v");
+(my $module = $Self->{name}) =~ s/.*t_altera_//;
+
+compile (
+    verilator_flags2 => ["--top-module ${module}"]
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_inz.cpp

@@ -0,0 +1,47 @@
+// -*- mode: C++; c-file-style: "cc-mode" -*-
+
+#include "Vt_tri_inz.h"
+
+Vt_tri_inz* tb = NULL;
+bool pass = true;
+
+double sc_time_stamp() {
+    return 0;
+}
+
+void checkone(const char* name, int got, int exp) {
+    if (got != exp) {
+        printf("%%Error: For %s got=%d exp=%d\n", name, got, exp);
+        pass = false;
+    }
+}
+
+void check(int d, int en, int exp0, int exp1, int expx, int expz) {
+    tb->d = d;
+    tb->d__en0 = en;
+    tb->eval();
+#ifdef TEST_VERBOSE
+    printf("Drive d=%d en=%d got0=%d/1=%d/x=%d/z=%d  exp0=%d/1=%d/x=%d/z=%d\n",
+           d, en, tb->ext0, tb->ext1, tb->extx, tb->extz, exp0, exp1, expx, expz);
+#endif
+    if (!expz) checkone("ext0", tb->ext0, exp0);
+    if (!expz) checkone("ext1", tb->ext1, exp1);
+    checkone("extx", tb->extx, expx);
+    checkone("extz", tb->extz, expz);
+}
+
+int main() {
+    Verilated::debug(0);
+    tb  = new Vt_tri_inz("tb");
+    check(0, 1,   1,0,0,0);
+    check(1, 1,   0,1,0,0);
+    check(0, 0,   0,0,0,1);
+
+    if (pass) {
+        VL_PRINTF("*-* All Finished *-*\n");
+        tb->final();
+    } else {
+        vl_fatal(__FILE__,__LINE__,"top", "Unexpected results from t_tri_inz\n");
+    }
+    return 0;
+}

test_regress/t/t_tri_inz.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("$FindBin::Bin/bootstrap.pl", @ARGV, $0); die; }
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2018 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# Lesser General Public License Version 3 or the Perl Artistic License
+# Version 2.0.
+
+$Self->{vlt} or $Self->skip("Verilator only test");
+
+compile (
+    make_top_shell => 0,
+    make_main => 0,
+    verilator_flags2 => ["--exe $Self->{t_dir}/$Self->{name}.cpp"],
+    );
+
+execute (
+    check_finished=>1,
+    );
+
+ok(1);
+1;

test_regress/t/t_tri_inz.v

@@ -0,0 +1,15 @@
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2018 by Wilson Snyder
+
+module top
+  (input d,
+   output ext0,
+   output ext1,
+   output extx,
+   output extz);
+
+   assign ext0 = (d === 1'b0);
+   assign ext1 = (d === 1'b1);
+   assign extx = (d === 1'bx);
+   assign extz = (d === 1'bz);
+endmodule